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publication number s29gl-a_00 revision a amendment 5 issue date january 11, 2006 s29gl-a mirrorbit? flash family s29gl064a, s29gl032a, and s29gl016a 64 megabit, 32 mega bit, and 16 megabit 3.0-volt only page mode flash memory featuring 200 nm mirrorbit process technology data sheet preliminary notice to readers: this document indicates st ates the current technical specifications regarding the spansion product(s) described herein. the preliminary status of this document in dicates that a product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require ma intaining efficiency and quality, this document may be revised by subseque nt versions or modifications due to changes in technical specifications.
ii s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary notice on data sheet designations spansion llc issues data sheets with advance in formation or pre liminary designations to advise readers of product information or intended specif ications throughout the product life cycle, in- cluding development, qualification, initial produc tion, and full production. in all cases, however, readers are encouraged to verify that they have the latest information before finalizing their de- sign. the following descriptions of spansion data sheet designations are presented here to high- light their presence and definitions. advance information the advance information designation indicates that spansion llc is developing one or more spe- cific products, but has not committed any design to production. information presented in a doc- ument with this designation is likely to change , and in some cases, development on the product may discontinue. spansion llc therefore places the following conditions upon advance informa- tion content: ?this document contains information on one or more products under development at spansion llc. the information is intended to help you evaluate this product. do not design in this product without con- tacting the factory. spansion llc reserves the righ t to change or discontinue work on this proposed product without notice.? preliminary the preliminary designation indicates that the pr oduct development has progressed such that a commitment to production has taken place. this designation covers several aspects of the prod- uct life cycle, including product qualification, in itial production, and the subsequent phases in the manufacturing process that occur before full pr oduction is achieved. ch anges to the technical specifications presented in a preliminary document should be expected while keeping these as- pects of production under consideration. spansion places the following conditions upon prelimi- nary content: ?this document states the current technical specifications regard ing the spansion product(s) described herein. the preliminary status of th is document indicates that produc t qualification has been completed, and that initial production has begun. due to the phases of the manufacturi ng process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifica- tions due to changes in technical specifications.? combination some data sheets will contain a co mbination of products with diff erent designations (advance in- formation, preliminary, or full production). this type of document will distinguish these products and their designations wherever necessary, typica lly on the first page, the ordering information page, and pages with dc characteristics table and ac erase and program table (in the table notes). the disclaimer on the first page refe rs the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of time such that no changes or only nominal changes are expected, the preliminary designatio n is removed from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or v io range. changes may also include those needed to clarify a descript ion or to correct a typographical error or incor- rect specification. spansion llc applies the following conditions to documents in this category: ?this document states the current technical specifications regard ing the spansion product(s) described herein. spansion llc deems the products to have been in sufficient production volume such that sub- sequent versions of this document are not expected to change. however, typogr aphical or specification corrections, or modifications to the va lid combinations o ffered may occur.? questions regarding these document designations may be directed to your local amd or fujitsu sales office.
this document contains information on one or more products under development at spansion llc. the information is intended to he lp you evaluate this product. do not design in this product without contacting the factory. spansion llc reserves the right to change or discontinue work on this pr oposed product without notice. publication number s29gl-a_00 revision a amendment 5 issue date january 11, 2006 distinctive characteristics architectural advantages ? single power supply operation ? 3-volt read, erase, and program operations ? manufactured on 200 nm mirrorbit process technology ? secured silicon sector region ? 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random electronic serial number, accessible through a command sequence ? may be programmed and locked at the factory or by the customer ? flexible sector architecture ? 64mb (uniform sector models): 128 32 kword (64 kb) sectors ? 64 mb (boot sector models): 127 32 kword (64 kb) sectors + 8 4kword (8kb) boot sectors ? 32 mb (uniform sector models): 64 32kword (64 kb) sectors ? 32 mb (boot sector models): 63 32kword (64 kb) sectors + 8 4kword (8kb) boot sectors ? 16 mb (boot sector models): 31 31kword (64 kb) sectors + 8 4kword (8 kb) boot sectors ? compatibility with jedec standards ? provides pinout and software compatibility for single- power supply flash, and su perior inadvertent write protection ? 100,000 erase cycles typical per sector ? 20-year data retention typical performance characteristics ? high performance ? 90 ns access time ? 4-word/8-byte page read buffer ? 25 ns page read times ? 16-word/32-byte write bu ffer which redu ces overall programming time for multiple-word updates ? low power consumption (typical values at 3.0 v, 5 mhz) ? 18 ma typical active read current ? 50 ma typical erase/program current ? 1 a typical standby mode current ? package options ?48-pin tsop ?56-pin tsop ? 64-ball fortified bga ? 48-ball fine-pitch bga ? 56-ball fine pitch bga (mcp-compatible for cellular handsets) software & hardware features ? software features ? program suspend & resu me: read other sectors before programming operation is completed ? erase suspend & resume : read/program other sectors before an erase operation is completed ? data# polling & toggle bits provide status ? cfi (common flash interface) compliant: allows host system to identify and ac commodate multiple flash devices ? unlock bypass program command reduces overall multiple-word programming time ? hardware features ? sector group protection: ha rdware-level method of preventing write operations within a sector group ? temporary sector unprotect: v id -level method of charging code in locked sectors ? wp#/acc input accelerates programming time (when high voltage is applie d) for greater throughput during system production. protects first or last sector regardless of sector protec tion settings on uniform sector models ? hardware reset input (reset#) resets device ? ready/busy# output (ry/ by#) detects program or erase cycle completion s29gl-a mirrorbit? flash family s29gl064a, s29gl032a, and s29gl016a 64 megabit, 32 megabit, and 16 megabit 3.0-volt only page mode flash memory featuring 200 nm mirrorbit process technology data sheet preliminary
2 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary general description the s29gl-a family of devices are 3.0-volt single-power flash memory manu - factured using 200 nm mirrorbit technology. the s29gl064a is a 64-mb device organized as 4,194,304 words or 8,388,608 bytes. the s29gl032a is a 32-mb device organized as 2,097,152 words or 4,194,304 bytes. the s29gl016a is a 16-mb device organized as 1,048,576 words or 2,097,152 bytes. depending on the model number, the devices have an 8-bit wide data bus only, 16-bit wide data bus only, or a 16-bit wide data bus that can also function as an 8-bit wide data bus by using the byte# input. the devices can be programmed either in the host system or in standard eprom programmers. access times as fast as 90 ns are available. note that each access time has a specific operating voltage range (v cc ) as specified in the product selector guide and the ordering information?s29gl016a , ordering information?s29gl032a , and ordering information?s29gl064a . package offerings include 48-pin tsop, 56-pin tsop, 48-ball fine-pitch bga an d 64-ball fortified bga, depending on model number. each device has separate chip enable (ce#), write enable (we#) and output enable (oe#) controls. each device requires only a single 3.0-volt power supply for both read and write functions. in addition to a v cc input, a high-voltage accelerated program (acc) feature provides shorter programming times through increased current on the wp#/acc input. this feature is intended to facilitate factory throughput during system production, but may also be used in the field if desired. the device is entirely comma nd set compatible with the jedec single-power- supply flash standard . commands are written to the device using standard microprocessor write timing. write cycles also internally latch addresses and data needed for the programming and erase operations. the sector erase architecture allows memory sectors to be erased and repro - grammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. device programming and erasure are initiated through command sequences. once a program or erase operation begins , the host system need only poll the dq7 (data# polling) or dq6 (toggle) status bits or monitor the ready/busy# (ry/by#) output to determine whether the op eration is complete. to facilitate programming, an unlock bypass mode reduces command sequence overhead by requiring only two write cycles to program data instead of four. hardware data protection measures include a low v cc detector that automat - ically inhibits write operations during power transitions. the hardware sector protection feature disables both program and erase operations in any combina - tion of sectors of memory. this can be achieved in-system or via programming equipment. the erase suspend/erase resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. the program suspend/program resume feature enables the host system to pause a program operation in a given sector to read any other sector and then complete the program operation. the hardware reset# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the de - vice, enabling the host system to read boot-up firmware from the flash memory device.
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 3 preliminary the device reduces power consumption in the standby mode when it detects specific voltage levels on ce# and rese t#, or when addresses are stable for a specified period of time. the write protect (wp#) feature protects the first or last sector by asserting a logic low on the wp#/acc pin or wp# pin, depending on model number. the protected sector is still protected even during accelerated programming. the secured silicon sector provides a 128-word/256- byte area for code or data that can be permanently protected. once this sector is protected, no further changes within the sector can occur. spansion mirrorbit flash technology combines years of flash memory manufac - turing experience to produce the highest levels of quality, reliability and cost effectiveness. the device electrically er ases all bits within a sector simulta - neously via hot-hole assisted erase. the data is programmed using hot electron injection.
4 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary table of contents notice on data sheet designations . . . . . . . . . . . ii product selector guide . . . . . . . . . . . . . . . . . . . . . 6 s29gl064a, s29gl032a, s29gl016a .............................................................6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 connection diagrams . . . . . . . . . . . . . . . . . . . . . . 8 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 12 logic symbol?s29gl064a (models r1, r2, r8, r9) .................................. 12 logic symbol?s29gl064a (model r5) ...........................................................13 logic symbol?s29gl064a (models r6, r7) .................................................13 logic symbol?s29gl064a (models w1, w2, we, and w4) ................. 14 logic symbol?s29gl032a (models r1, r2) ................................................. 14 logic symbol?s29gl032a (models r3, r4) ................................................. 14 logic symbol?s29gl032a (models w1,w2,w3, and w4) ......................15 logic symbol?s29gl016a (models r1, r2) ...................................................15 logic symbol?s29gl016a (models w3,w4) ...............................................15 ordering information?s29gl016a . . . . . . . . . . . 16 s29gl016a standard products ............... ......................................................... 16 table 1. s29gl016a ordering options .................................... 16 ordering information?s29gl032a . . . . . . . . . . . 17 s29gl032a standard products .........................................................................17 table 2. s29gl032a ordering options .................................... 17 ordering information?s29gl064a . . . . . . . . . . . 18 s29gl064a standard products ....................................................................... 18 table 3. s29gl064a valid combinations ................................. 18 device bus operations . . . . . . . . . . . . . . . . . . . . . 19 table 4. device bus operations ............................................. 19 word/byte configuration .................................................................................20 requirements for reading array data ......................................................... 20 writing commands/command sequences ................................................. 20 standby mode ........................................................................................................ 21 automatic sleep mode ...................................................................................... 22 reset#: hardware reset pin ......................................................................... 22 output disable mode ........................................................................................ 22 table 5. s29gl016a (model r1, w1 ) top boot sector addresses 23 table 6. s29gl016a (model r2, w2) bottom boot sector addresses .............................................. 24 table 7. s29gl032a (models r1, r2, w1, w2) sector addresses 25 table 8. s29gl032a (model r3, w3 ) top boot sector addresses 26 table 9. s29gl032a (model r4, w4) bottom boot sector addresses .............................................. 27 table 10. s29gl064a (models r1, r2, r8, r9, w1, w2) sector addresses ........................................................................... 28 table 11. s29gl064a (model r3, w3) top boot sector addresses ................................................... 30 table 12. s29gl064a (model r4, w4) b ottom boot sector addresses ................................................ 32 table 13. s29gl064a (model r5) sector addresses ................. 34 table 14. s29gl064a (models r6, r7) sector addresses .......... 36 autoselect mode ..................................................................................................37 table 15. autoselect codes, (high voltage method) ................. 38 sector group protection and unprotection ...............................................38 table 16. s29gl016a (model r1, 01 , w1) sector group protection/ unprotection addresses ........................................................ 39 table 17. s29gl016a (model r2, 02 , w2) sector group protection/ unprotection addresses ........................................................ 39 table 18. s29gl032a (models r1, r2, w1, w2) sector group protection/unprotection addresses ......................................... 39 table 19. s29gl032a (model r3, w3) sector grou p protection/ unprotection address table .................................................. 40 table 20. s29gl032a (model r4, w4) sector grou p protection/ unprotection address table ................................................... 40 table 21. s29gl064a (models r1, r2, r8, r9, w1, w2) sector group protection/unprotection addresses ......................................... 40 table 22. s29gl064a (model r3, w3) top boot sector protection/ unprotection addresses ........................................................ 41 table 23. s29gl064a (model r4, w4) bottom boot sector protection/unprotection addresses ......................................... 41 table 24. s29gl064a (model r5 ) sector group protection/ unprotection addresses ........................................................ 42 table 25. s29gl064a (models r6, r7) sector group protection/ unprotection addresses ........................................................ 42 temporary sector group unprotect ............................................................43 figure 1. temporary se ctor group unprotect operation ............ 43 figure 2. in-system sector group protect/unprotect algorithms 44 secured silicon sector flash memory region ............................................ 45 write protect (wp#) ........................................................................................ 46 hardware data protection ............................................................................... 46 table 26. cfi query identification string ................................ 48 table 27. system interface string .......................................... 48 table 29. primary vendor-specific ex tended query .................. 49 command definitions . . . . . . . . . . . . . . . . . . . . . 50 reading array data ............................................................................................50 reset command .................................................................................................. 50 autoselect command sequence ...................................................................... 51 enter/exit secured silicon sector command sequence ........................... 51 figure 3. write buffer programming operation......................... 55 figure 4. program operation ................................................. 56 program suspend/program resume command sequence ..................... 56 figure 5. program suspend/program resume .......................... 57 chip erase command sequence .................................................................... 57 figure 6. erase operation ..................................................... 59 erase suspend/erase resume commands ................................................... 59 command definitions ......................................................................................... 61 table 30. command definitions (x16 mode, byte# = v ih ) ........ 61 table 31. command definitions (x8 mode, byte# = v il ) .......... 62 write operation status .....................................................................................63 dq7: data# polling ............................................................................................. 63 figure 7. data# polling algorithm .......................................... 64 ry/by#: ready/busy# ........................................................................................ 64 dq6: toggle bit i .................................................................................................65 figure 8. toggle bit algorithm ............................................... 66 dq2: toggle bit ii ................................................................................................67 reading toggle bits dq6/dq2 ....................................................................... 67 dq5: exceeded timing limits ......................................................................... 67 dq3: sector erase timer .................................................................................68 dq1: write-to-buffer abort ............................................................................68 table 32. write operation status ........................................... 68 absolute maximum ratings . . . . . . . . . . . . . . . . 69 figure 9. maximum negative overshoot waveform .................. 69 figure 10. maximum positive overshoot waveform .................. 69 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . 70 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 71 cmos compatible ............................................................................................... 71 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 11. test setup ........................................................... 72 table 33. test specifications ................................................. 72 figure 12. input waveforms and measurement levels .............. 72 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 73 table 34. read-only operations-s29gl064a only .................... 73 table 35. read-only operations-s29gl032a only .................... 73 table 36. read-only operation-s29gl016a only ..................... 74
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 5 preliminary figure 13. read operation timings ......................................... 74 figure 14. page read timings ................................................ 75 table 37. hardware reset (reset#) ...................................... 75 figure 15. reset timings ....................................................... 75 table 38. erase and program operations-s29gl064a ............... 76 table 39. erase and program operations-s29gl032a only ....... 77 table 40. erase and program operations-s29gl016a only ....... 78 figure 16. program operation timings .................................... 79 figure 17. accelerated program timing diagram....................... 79 figure 18. chip/sector erase operation timings ....................... 80 figure 19. data# polling timings (during embedded algorithms) 80 figure 20. toggle bit timings (during embedded algorithms)..... 81 figure 21. dq2 vs. dq6 ........................................................ 81 table 41. temporary sector unprotect ................................... 81 figure 22. temporary sector gr oup unprotect timing diagram .. 82 figure 23. sector grou p protect and unprotect timing diagram.. 82 table 42. alternate ce# controlled erase and program operations- s29gl064a ........................................................................ 83 table 43. alternate ce# controlled erase and program operations- s29gl032a ........................................................................ 84 table 44. alternate ce# controlled erase and program operations- s29gl016a ........................................................................ 85 figure 24. alternate ce# controlled write (erase/program) opera- tion timings ........................................................................ 86 erase and programming performance . . . . . . . 87 table 45. tsop pin and bga package capacitance ................... 87 physical dimensions . . . . . . . . . . . . . . . . . . . . . . . 88 ts048?48-pin standard thin small outline package (tsop) .............88 ts056?56-pin standard thin small outline package (tsop) ..............89 laa064?64-ball fortified ball grid array (bga) ...................................90 vbn048?48-ball fine-pitch ball grid array (bga) 10x 6 mm package ................................................................................................ 91 vbk048?ball fine-pitch ball grid array (bga) 8.15x 6.15 mm package ........................................................................................ 92 vbu056?ball fine-pitch ball grid array (bga) 9 x 7 mm package .. 93 revision summary . . . . . . . . . . . . . . . . . . . . . . . . 94 revision a (october 13, 2004) ........................................................................ 94 revision a1 (december 17, 2004) ................................................................... 94 revision a2 (january 28, 2005) ....................................................................... 94 revision a3 (april 22, 2005) ............................................................................ 94 revision a4 (july 29, 2005) ...............................................................................94 revision a5 (january 4, 2006) .......................................................................... 94
6 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary product selector guide s29gl064a, s29gl032a, s29gl016a part number s29gl064a s29gl032a s29gl016a speed option 90 10 11 90 10 11 90 10 max. access time (ns) 90 100 110 90 100 110 90 100 max. ce# access time (ns) 90 100 110 90 100 110 90 100 max. page access time (ns) 25 30 30 25 30 30 25 30 max. oe# access time (ns) 25 30 30 25 30 30 25 30
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 7 preliminary block diagram note: **a max gl064a = a21. **a max gl032a = a20. **a max gl016a = a19. input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss we# wp#/acc byte# ce# oe# stb stb dq15 ? dq0 (a-1) sector switches ry/by# reset# data latch y-gating cell matrix address latch a max **?a0
8 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary connection diagrams special package handling instructions special handling is required for flash memory products in molded packages (tsop and bga). the package and/or data integrity may be compromised if the package body is exposed to temperatur es above 150c for prolonged periods of time. notes: 1. pin 9 is a21, pin 13 is acc, pin 14 is wp#, pin 15 is a19, and pin 47 is v io on s29gl064a (models r6, r7). 2. pin 13 is nc on s29gl032a, and s29gl016a. 3. pin 10 is nc on s29gl016a. note: pin 15 is nc on s29gl032a. 1 16 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 48 33 47 46 45 44 43 42 41 40 39 38 37 36 35 34 25 32 31 30 29 28 27 26 a15 a18 a14 a13 a12 a11 a10 a9 a8 a19 1 a20 3 we# reset# a21 1,2 wp#/acc 1 ry/by# 1 a1 a17 a7 a6 a5 a4 a3 a2 a16 dq2 byte# 1 v ss dq15/a-1 dq7 dq14 dq6 dq13 dq9 dq1 dq8 dq0 oe# v ss ce# a0 dq5 dq12 dq4 v cc dq11 dq3 dq10 48-pin standard tsop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 nc nc a15 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# reset# a21 1 wp#/acc ry/by# a18 a17 a7 a6 a5 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 nc nc a16 byte# v ss dq15/a-1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v cc dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 23 24 25 26 27 28 a4 a3 a2 a1 nc nc 34 33 32 31 30 29 oe# v ss ce# a0 nc v io 56-pin standard tsop
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 9 preliminary notes: 1. ball d8 and ball f1 are nc on s29gl064a (models r3, r4). 2. ball f7 is nc on s29gl064a (model r5). 3. ball c5 is nc on s29gl032a and s29gl016a. 4. ball d4 is nc on s29gl016a. a2 c2 d2 e2 f2 g2 h2 a3 c3 d3 e3 f3 g3 h3 a4 c4 d4 e4 f4 g4 h4 a5 c5 d5 e5 f5 g5 h5 a6 c6 d6 e6 f6 g6 h6 a7 c7 d7 e7 f7 g7 h7 dq15/a-1 v ss byte# 2 a16 a15 a14 a12 a13 dq13 dq6 dq14 dq7 a11 a10 a8 a9 v cc dq4 dq12 dq5 a19 a21 3 reset# we# dq11 dq3 dq10 dq2 a20 4 a18 wp#/acc ry/by# dq9 dq1 dq8 dq0 a5 a6 a17 a7 oe# v ss ce# a0 a1 a2 a4 a3 a1 c1 d1 e1 f1 g1 h1 nc nc v io 1 nc nc nc nc nc a8 c8 b2 b3 b4 b5 b6 b7 b1 b8 d8 e8 f8 g8 h8 nc nc nc v ss v io 1 nc nc nc 64-ball fortified bga top view, balls facing down
10 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary note: mcp-compatible connection diagram for cellular handsets only dq8 rfu a3 a7 a2 wp/acc a4 we# a5 a8 a6 a11 a7 dq2 h3 h2 dq11 h4 rfu h5 dq5 h6 dq14 h7 rfu g1 dq0 g2 dq10 g3 rfu g5 dq12 g6 dq7 g7 ce# f1 oe# f2 dq3 f4 dq9 f3 dq4 f5 dq13 f6 dq15 f7 rfu f8 a2 c1 a5 c2 ry/by# c4 a18 c3 rfu c5 a9 c6 a13 c7 rfu c8 a3 b1 a6 b2 rst b4 rfu b3 rfu b5 a19 b6 a12 b7 a15 b8 dq6 e6 rfu e7 a16 e8 a0 e1 dq1 e3 a10 d6 a14 d7 rfu d8 a1 d1 a4 d2 a17 d3 rfu legend e2 v ss g4 v cc g8 v ss 56-ball fine-pitch ball grid array top view, balls facing down
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 11 preliminary notes: 1. ball f6 is v io on s29gl064a (model r5). 2. ball c4 is nc on s29gl032a and s29gl016a. 3. ball d3 is nc on s29gl016a. a1 b1 c1 d1 e1 f1 g1 h1 a2 b2 c2 d2 e2 f2 g2 h2 a3 b3 c3 d3 e3 f3 g3 h3 a4 b4 c4 d4 e4 f4 g4 h4 a5 b5 c5 d5 e5 f5 g5 h5 a6 b6 c6 d6 e6 f6 g6 h6 dq15/a-1 v ss byte# 1 a16 a15 a14 a12 a13 dq13 dq6 dq14 dq7 a11 a10 a8 a9 v cc dq4 dq12 dq5 a19 a21 2 reset# we# dq11 dq3 dq10 dq2 a20 3 a18 wp#/acc ry/by# dq9 dq1 dq8 dq0 a5 a6 a17 a7 oe# v ss ce# a0 a1 a2 a4 a3 48-ball fine-pitch bga to p v i ew, b a l ls fa c i n g d o w n
12 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary pin descriptions a21?a0 = 22 address inputs a20?a0 = 21 address inputs a19?a0 = 20 address inputs dq7?dq0 = 8 data inputs/outputs dq14?dq0 = 15 data inputs/outputs dq15/a-1 = dq15 (data input/output, word mode), a-1 (lsb address input, byte mode) ce# = chip enable input oe# = output enable input we# = write enable input wp#/acc = hardware write protect input/programming acceleration input acc = acceleration input wp# = hardware write protect input reset# = hardware reset pin input ry/by# = ready/busy output byte# = selects 8-bit or 16-bit mode v cc = 3.0 volt-only single power supply (see product selector guide for speed options and voltage supply tolerances) v ss = device ground nc = pin not connected internally v io = output buffer power logic symbols logic symbol?s29gl064a (m odels r1, r2, r8, r9) 22 16 or 8 dq15?dq0 (a-1) a21?a0 ce# oe# we# reset# ry/by# wp#/acc byte# v io
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 13 preliminary logic symbol?s29gl064a (models r3, r4) logic symbol?s29gl064a (model r5) logic symbol?s29gl064a (models r6, r7) 22 16 or 8 dq15?dq0 (a-1) a21?a0 ce# oe# we# reset# ry/by# wp#/acc byte# 22 16 dq15?dq0 a21?a0 ce# oe# we# reset# ry/by# acc v io 22 16 dq15?dq0 a21?a0 ce# oe# we# reset# acc wp# v io reset#
14 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary logic symbol?s29gl064a (mod els w1, w2, we, and w4) logic symbol?s29gl032a (models r1, r2) logic symbol?s29gl032a (models r3, r4) 22 16 dq15?dq0 a21?a0 ce# oe# we# wp#/acc reset# 21 16 or 8 dq15?dq0 (a-1) a20?a0 ce# oe# we# reset# ry/by# wp#/acc byte# v io 21 16 or 8 dq15?dq0 (a-1) a20?a0 ce# oe# we# reset# ry/by# wp#/acc byte#
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 15 preliminary logic symbol?s29gl032a (models w1,w2,w3, and w4) logic symbol?s29gl016a (models r1, r2) logic symbol?s29gl016a (models w3,w4) 21 16 dq15?dq0 a20?a0 ce# oe# we# reset# ry/by# wp#/acc 20 16 or 8 dq15?dq0 (a-1) a19?a0 ce# oe# we# reset# ry/by# wp#/acc byte# 20 16 dq15?dq0 a19?a0 ce# oe# we# reset# ry/by# wp#/acc
16 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary ordering information?s29gl016a s29gl016a standard products standard products are available in several packages and operating ranges. the order number (valid combinat ion) is formed by a combination of the following: s29gl016a 10 t a i r1 0 packing type 0= tray 2 = 7-inch tape and reel 3 = 13-inch tape and reel model number r1 = x8/x16, v cc =3.0 ? 3.6 v, top boot sector device, top two address sectors protected when wp#/acc=v il r2 = x8/x16, v cc =3.0 ? 3.6 v, bottom boot sector device, bottom two address sectors protected when wp#/acc=v il 01 = x8/x16, vcc = 2.7 - 3.6 v, top boot sector device, top two address sectors protected when wp#/acc = v il 02 = x8/x16, vcc = 2.7 - 3.6 v, bottom boot sector device, bottom two address sectors protected when wp#/acc = v il w1 = x16, v cc =2.7 ? 3.6 v, 56-ball fbga, top boot sector device * w2 = x16, v cc =2.7 ? 3.6 v, 56-ball fbga, bottom boot sector device * *w1 and w2 are mcp-compatible packages for cellular handsets only temperature range i = industrial (?40c to +85c) package material set a= standard f= pb-free package type t = thin small outline package (tsop) standard pinout b = fine-pitch ball-grid array package f = fortified ball-grid array package speed option see product selector guide and valid combinations device number/description s29gl016a 3.0 volt-only, 16 megabit page-mode flash memory manufactured on 200 nm mirrorbit? process technology. ta b l e 1 . s29gl016a ordering options s29gl016a valid combinations package description (notes) device number speed option package, material, & temperature range model number packing type (note 1 ) s29gl016a 90, 10 tai, tfi r1, r2 0, 3 ts048 ( note 2 ) tsop bai, bfi 0, 2, 3 vbk048 ( note 3 ) fine-pitch bga fai, ffi laa064 ( note 3 ) fortified bga 10 bai, bfi w1, w2 vbu056 ( note 3 ) fine-pitch bga (for cellular handsets only) 10 tai, tfi 01, 02 0, 3 ts048 ( note 2 ) tsop bai, bfi 0, 2, 3 vbk048 ( note 3 ) fine-pitch bga fai, ffi laa064 ( note 3 ) fortified bga notes: 1. type 0 is standard. specify others as required: tsops can be packed in types 0 and 3; bgas can be packed in types 0, 2, or 3. 2. tsop package marking omits packing type designator from ordering part number. 3. bga package marking omits leading s29 and packing type designator from ordering part number. valid combinations valid combinations list configuratio ns planned to be supported in volume for this device. consult your local sales office to confirm availability of specific valid co mbinations and to check on newly released combinations.
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 17 preliminary ordering information?s29gl032a s29gl032a standard products standard products are available in several packages and operating ranges. the order number (valid combinat ion) is formed by a combination of the following: s29gl032a 90 t a i r1 0 packing type 0= tray 2 = 7-inch tape and reel 3 = 13-inch tape and reel model number r1 = x8/x16, v cc =3.0 ? 3.6 v, uniform sector device, highest address sector protected when wp#/acc=v il r2 = x8/x16, v cc =3.0 ? 3.6 v, uniform sector device, lowest address sector protected when wp#/acc=v il r3 = x8/x16, v cc =3.0 ? 3.6 v, top boot sector device, top two address sectors protected when wp#/acc=v il r4 = x8/x16, v cc =3.0 ? 3.6 v, bottom boot sector device, bottom two address sectors protected when wp#/acc=v il w1 = x16 v cc =2.7 ? 3.6 v, 56-ball fbga, uniform sector device, highest address sector protected when wp#/acc=v il * w2 = x16 v cc =2.7 ? 3.6 v, 56-ball fbga, uniform sector device, lowest address sector protected when wp#/acc=v il * w3 = x16, v cc =2.7 ? 3.6 v, 56-ball fbga, top boot sector device * w4 = x16, v cc =2.7 ? 3.6 v, 56-ball fbga, bottom boot sector device * *w1, w2, w3 and w4 are mcp-compatible packages for cellular handsets only temperature range i = industrial (?40c to +85c) package material set a= standard f= pb-free package type t = thin small outline package (tsop) standard pinout b = fine-pitch ball-grid array package f = fortified ball-grid array package speed option see product selector guide and valid combinations device number/description s29gl032a 32 megabit page-mode flash memory manufactured using 200 nm mirrorbit? process technology, 3.0 volt-only read, program, and era se ta b l e 2 . s29gl032a ordering options s29gl032a valid combinations package description (notes) device number speed option package, material, & temperature range model number packing type s29gl032a 90, 10, 11 tai,tfi r1, r2 0,2,3 ( note 1 ) ts056 ( note 2 ) tsop fai,ffi laa064 ( note 3 ) fortified bga tai,tfi r3,r4 ts048 ( note 2 ) tsop bai,bfi vbk048 ( note 3 ) fine-pitch bga fai,ffi laa064 ( note 3 ) fortified bga 10, 11 bai,bfi w1,w2,w3,w4 vbu056 ( note 3 ) fine-pitch bga (for cellular handsets only) notes: 1. type 0 is standard. specify others as required: tsops can be packed in types 0 and 3; bgas can be packed in types 0, 2, or 3. 2. tsop package marking omits pa cking type designator from ordering part number. 3. bga package marking omits leading s29 and packing type designator from ordering part number. valid combinations valid combinations list co nfigurations planned to be supported in volume for this device. consult your local sa les office to confirm availability of specific valid combinatio ns and to check on newly released combinations.
18 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary ordering information?s29gl064a s29gl064a standard products standard products are available in seve ral packages and operating ranges. the order number (valid combination) is formed by a combination of the following: s29gl064a 90 t a i r1 2 packing type 0 = tray 2 = 7-inch tape and reel 3 = 13-inch tape and reel model number r1 = x8/x16, v cc =3.0 ? 3.6 v, uniform sector device, highest address sector protected when wp#/acc=v il r2 = x8/x16, v cc =3.0 ? 3.6 v, uniform sector device, lowest address sector protected when wp#/acc=v il r3 = x8/x16, v cc =3.0 ? 3.6 v, top boot sector device, top two address sectors protected when wp#/acc=v il r4 = x8/x16, v cc =3.0 ? 3.6 v, bottom boot sector device, bottom two address sectors protected when wp#/acc=v il r5 = x16, v cc =3.0 ? 3.6 v, uniform sector device r6 = x16, v cc =3.0 ? 3.6 v, uniform sector device, highest address sector protected when wp#=v il r7 = x16, v cc =3.0 ? 3.6 v, uniform sector device, lowest address sector protected when wp#=v il r8 = x8/x16, v cc =3.0 ? 3.6 v, uniform sector device, highest address sector protected when wp#=v il, tso48 only r9 = x8/x16, v cc =3.0 ? 3.6 v, uniform sector device, lowest address sector protected when wp#=v il, tso48 only w1 = x16 v cc =2.7 ? 3.6 v, 56-ball fbga, uniform sector device, highest address sector protected when wp#/acc=v il * w2 = x16 v cc =2.7 ? 3.6 v, 56-ball fbga, uniform sector device, lowest address sector protected when wp#/acc=v il * w3 = x16, v cc =2.7 ? 3.6 v, 56-ball fbga, top boot sector device * w4 = x16, v cc =2.7 ? 3.6 v, 56-ball fbga, bottom boot sector device * *w1, w2, w3 and w4 are mcp-compatible packages for cellular handsets only temperature range i = industrial (?40c to +85c) package material set a= standard f= pb-free package type t = thin small outline package (tsop) standard pinout b = fine-pitch ball-grid array package f = fortified ball-grid array package speed option see product selector guide and valid combinations device number/description s29gl064a, 64 megabit page-mode flash memory manufactured using 200 nm mirrorbit? process technology, 3.0 volt-only read, progr am, and erase table 3. s29gl064a valid combinations s29gl064a valid combinations package description device number speed option package, material & temperature range model number packing type s29gl064a 90, 10, 11 tai, tfi r3, r4, r6, r7, r8, r9 0, 2, 3 ( note 1 ) ts048 ( note 2 ) tsop r1, r2 ts056 ( note 2 ) tsop bai, bfi r3, r4, r5 vbn048 ( note 3 ) fine-pitch bga fai, ffi r1, r2, r3, r4, r5 laa064 ( note 3 ) fortified bga 10, 11 bai,bfi w1, w2, w3, w4 vbh064 ( note 3 ) fine-pitch bga (for cellular handsets only) notes: 1. type 0 is standard. specify others as required: tsops can be packed in types 0 and 3; bgas can be packed in types 0, 2, or 3. 2. tsop package marking omits packing type designator from ordering part number. 3. bga package marking omits leading s29 and packing type designator from ordering part number. valid combinations valid combinations list conf igurations planned to be supported in volume for this device. consult your local sales office to confirm ava ilability of specific valid combinations and to check on newly released combinations.
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 19 preliminary device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command regis - ter itself does not occupy any addressa ble memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. ta b l e 4 lists the device bus operations, the inputs and control levels they require, and the resulting output. the following subsections describe each of these operations in further detail. legend: l = logic low = v il , h = logic high = v ih , v id = 11.5?12.5 v, v hh = 11.5?12.5 v, x = don?t care, sa = sector address, a in = address in, d in = data in, d out = data out notes: 1. addresses are amax:a0 in word mode; amax:a-1 in by te mode. sector addresses are amax:a15 in both modes. 2. the sector protect and sector unprotect functions may also be implemented via programming equipment. see the ?sector group pr otection and unprotection? section. 3. if wp# = vil, the first or last sector remains protected (for uniform sector devices), and the two outer boot sectors are pro tected (for boot sector devices). if wp# = vih, the first or last sector, or th e two outer boot sectors are protected or unprotected as determin ed by the method described in sector group protection and unprotection on page 38 . all sectors are unprotected when shipped from the factory (the secured silicon sector may be factory protected depending on version ordered.) 4. d in or d out as required by command sequence, data po lling, or sector protect algorithm (see figure 7, on page 64 ). table 4. device bus operations operation ce# oe# we# reset# wp# acc addresses ( note 1 ) dq0? dq7 dq8?dq15 byte# = v ih byte# = v il read l l h h x x a in d out d out dq8?dq14 = high-z, dq15 = a-1 write (program/erase) l h l h ( note 3 )x a in ( note 4 )( note 4 ) accelerated program l h l h ( note 3 )v hh a in ( note 4 )( note 4 ) standby v cc 0.3 v x x v cc 0.3 v x h x high-z high-z high-z output disable l h h h x x x high-z high-z high-z reset x x x l x x x high-z high-z high-z sector group protect (note 2) lhlv id hx sa, a6 =l, a3=l, a2=l, a1=h, a0=l ( note 4 )x x sector group unprotect ( note 2 ) lhlv id hx sa, a6=h, a3=l, a2=l, a1=h, a0=l ( note 4 )x x temporary sector group unprotect x x x v id hx a in ( note 4 )( note 4 )high-z
20 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary word/byte configuration the byte# pin controls whether the device data i/o pins operate in the byte or word configuration. if the byte# pin is set at logic 1 , the device is in word con - figuration, dq0?dq15 are active and controlled by ce# and oe#. if the byte# pin is set at logic 0 , the device is in byte configuration, and only data i/o pins dq0?dq7 are active and controlled by ce# and oe#. the data i/ o pins dq8?dq14 are tri-stated, and the dq15 pin is used as an input for the lsb (a-1) address function. requirements for reading array data to read array data from the outputs, the system must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output control and gates array data to the output pins. we# should remain at v ih . the internal state machine is set for re ading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the mem - ory content occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. see reading array data on page 50 for more information. refer to the ac read- only operations table for timing specific ations and the timing diagram. refer to the dc characteristics table for the active current specification on reading array data. page mode read the device is capable of fast page mode read and is compatible with the page mode mask rom read operation. this mo de provides faster read access speed for random locations within a page. the page size of the device is 4 words/8 bytes. the appropriate page is selected by the higher address bits a(max)?a2. address bits a1?a0 in word mode (a1?a-1 in byte mode) determine the specific word within a page. this is an asynchronous operation; the microprocessor sup - plies the specific word location. the random or initial page access is equal to t acc or t ce and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to t pacc . when ce# is deasserted and reasserted for a subsequent access, the access time is t acc or t ce . fast page mode accesses are obtained by keeping the read-page addresses constant and changing the intra-read page addresses. writing commands/command sequences to write a command or command sequence (which includes programming data to the device and erasing sectors of me mory), the system must drive we# and ce# to v il , and oe# to v ih . the device features an unlock bypass mode to facilitate faster programming. once the device enters the unlock bypass mode, only two write cycles are re - quired to program a word , instead of four. the word program command sequence on page 51 contains details on programming data to the device using both standard and unlock bypass command sequences.
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 21 preliminary an erase operation can erase one sector, multiple sectors, or the entire device. ta b l e s 7 ? 25 indicate the address space that each sector occupies. refer to the dc characteristics table for the active current specification for the write mode. the ac characteristics section contains timing specification tables and timing diagrams for write operations. write buffer write buffer programming allows the sy stem write to a maximum of 16 words/ 32 bytes in one programming operation. this results in faster effective program - ming time than the standard programming algorithms. see write buffer on page 21 for more information. accelerated program operation the device offers accelerated program op erations through the acc function. this is one of two functions provided by the wp#/acc or acc pin, depending on model number. this function is primarily intended to allow faster manufacturing throughput at the factory. if the system asserts v hh on this pin, the device automatically enters the afore - mentioned unlock bypass mode, temporar ily unprotects any protected sector groups, and uses the higher voltage on the pin to reduce the time required for program operations. the system would use a two-cycle program command se - quence as required by the un lock bypass mode. removing v hh from the wp#/ acc or acc pin, depending on model number, returns the device to normal op - eration. note that the wp#/acc or acc pin must not be at v hh for operations other than accelerated programming, or device damage may result. wp# con - tains an internal pullup; when unconnected, wp# is at v ih . autoselect functions if the system writes the autoselect command sequence, the device enters the autoselect mode. the system can then read autoselect codes from the internal register (which is separate from the me mory array) on dq7?dq0. standard read cycle timings apply in this mode. refer to autoselect mode on page 37 and au - toselect command sequence on page 51 for more information. standby mode when the system is not reading or writin g to the device, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high im pedance state, inde pendent of the oe# input. the device enters the cmos standby mo de when the ce# and reset# pins are both held at v io 0.3 v. (note that this is a more restricted voltage range than v ih .) if ce# and reset# are held at v ih , but not within v io 0.3 v, the device is in the standby mode, but the standby cu rrent is greater. the device requires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or programming, the device draws ac - tive current until the operation is completed. refer to the dc characteristics on page 71 for the standby current specification.
22 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. the de - vice automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is indepe ndent of the ce#, we#, and oe# con - trol signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. refer to the dc characteristics on page 71 for the automatic sleep mode current specification. reset#: hardware reset pin the reset# pin provides a hardware meth od of resetting the device to reading array data. when the reset# pin is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal st ate machine to reading array data. the op - eration that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. current is reduced for the duration of th e reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current (i cc5 ). if reset# is held at v il but not within v ss 0.3 v, the standby current is greater. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firm - ware from the flash memory. refer to the ac characteristics tables for reset# parameters and to figure 15, on page 75 for the timing diagram. output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins are placed in the high impedance state.
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 23 preliminary table 5. s29gl016a (model r1, w1) top boot sector addresses sector a19?a12 sector size (kb/ kwords) 8-bit address range 16-bit address range sector a19?a12 sector size (kb/ kwords) 8-bit address range 16-bit address range sa0 000000xxx 64/32 000000h?00ffffh 00000h?07fffh sa20 010100xxx 64/32 140000h?14ffffh a0000h?a7fffh sa1 000001xxx 64/32 010000h?01ffffh 08000h?0ffffh sa21 010101xxx 64/32 150000h?15ffffh a8000h?affffh sa2 000010xxx 64/32 020000h?02ffffh 10000h?17fffh sa22 010110xxx 64/32 160000h?16ffffh b0000h?b7fffh sa3 000011xxx 64/32 030000h?03ffffh 18000h?1ffffh sa23 010111xxx 64/32 170000h?17ffffh b8000h?bffffh sa4 000100xxx 64/32 040000h?04ffffh 20000h?27fffh sa24 011000xxx 64/32 180000h?18ffffh c0000h?c7fffh sa5 000101xxx 64/32 050000h?05ffffh 28000h?2ffffh sa25 011001xxx 64/32 190000h?19ffffh c8000h?cffffh sa6 000110xxx 64/32 060000h?06ffffh 30000h?37fffh sa26 011010xxx 64/32 1a0000h?1affffh d0000h?d7fffh sa7 000111xxx 64/32 070000h?07ffffh 38000h?3ffffh sa27 011011xxx 64/32 1b0000h?1bffffh d8000h?dffffh sa8 001000xxx 64/32 080000h?08ffffh 40000h?47fffh sa28 011000xxx 64/32 1c0000h?1cffffh e0000h?e7fffh sa9 001001xxx 64/32 090000h?09ffffh 48000h?4ffffh sa29 011101xxx 64/32 1d0000h?1dffffh e8000h?effffh sa10 001010xxx 64/32 0a0000h?0affffh 50000h?57fffh sa30 011110xxx 64/32 1e0000h?1effffh f0000h?f7fffh sa11 001011xxx 64/32 0b0000h?0bffffh 58000h?5ffffh sa31 111111000 8/4 1f0000h?1f1fffh 0f8000h?0f8fffh sa12 001100xxx 64/32 0c0000h?0cffffh 60000h?67fffh sa32 111111001 8/4 1f2000h?1f3fffh 0f9000h?0f9fffh sa13 001101xxx 64/32 0d0000h?0dffffh 68000h?6ffffh sa33 111111010 8/4 1f4000h?1f5fffh 0fa000h?0fafffh sa14 001101xxx 64/32 0e0000h?0effffh 70000h?77fffh sa34 111111011 8/4 1f6000h?1f7fffh 0fb000h?0fbfffh sa15 001111xxx 64/32 0f0000h?0fffffh 78000h?7ffffh sa35 111111100 8/4 1f8000h?1f9fffh 0fc000h?0fcfffh sa16 010000xxx 64/32 100000h?00ffffh 80000h?87fffh sa36 111111101 8/4 1fa000h?1fbfffh 0fd000h?0fdfffh sa17 010001xxx 64/32 110000h?11ffffh 88000h?8ffffh sa37 111111110 8/4 1fc000h?1fdfffh 0fe000h?0fefffh sa18 010010xxx 64/32 120000h?12ffffh 90000h?97fffh sa38 111111111 8/4 1fe000h?1fffffh 0ff000h?0fffffh sa19 010011xxx 64/32 130000h?13ffffh 98000h?9ffffh
24 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary table 6. s29gl016a (model r2, w2) bottom boot sector addresses sector a19?a12 sector size (kb/ kwords) 8-bit address range 16-bit address range sector a19?a12 sector size (kb/ kwords) 8-bit address range 16-bit address range sa0 000000000 8/4 000000h?001fffh 00000h?00fffh sa19 001100xxx 64/32 0c0000h?0cffffh 60000h?67fffh sa1 000000001 8/4 002000h?003fffh 01000h?01fffh sa20 001101xxx 64/32 0d0000h?0dffffh 68000h?6ffffh sa2 000000010 8/4 004000h?005fffh 02000h?02fffh sa21 001101xxx 64/32 0e0000h?0effffh 70000h?77fffh sa3 000000011 8/4 006000h?007fffh 03000h?03fffh sa22 001111xxx 64/32 0f0000h?0fffffh 78000h?7ffffh sa4 000000100 8/4 008000h?009fffh 04000h?04fffh sa23 010000xxx 64/32 100000h?00ffffh 80000h?87fffh sa5 000000101 8/4 00a000h?00bfffh 05000h?05fffh sa24 010001xxx 64/32 110000h?11ffffh 88000h?8ffffh sa6 000000110 8/4 00c000h?00dfffh 06000h?06fffh sa25 010010xxx 64/32 120000h?12ffffh 90000h?97fffh sa7 000000111 8/4 00e000h?00fffffh 07000h?07fffh sa26 010011xxx 64/32 130000h?13ffffh 98000h?9ffffh sa8 000001xxx 64/32 010000h?01ffffh 08000h?0ffffh sa27 010100xxx 64/32 140000h?14ffffh a0000h?a7fffh sa9 000010xxx 64/32 020000h?02ffffh 10000h?17fffh sa28 010101xxx 64/32 150000h?15ffffh a8000h?affffh sa10 000011xxx 64/32 030000h?03ffffh 18000h?1ffffh sa29 010110xxx 64/32 160000h?16ffffh b0000h?b7fffh sa11 000100xxx 64/32 040000h?04ffffh 20000h?27fffh sa30 010111xxx 64/32 170000h?17ffffh b8000h?bffffh sa12 000101xxx 64/32 050000h?05ffffh 28000h?2ffffh sa31 011000xxx 64/32 180000h?18ffffh c0000h?c7fffh sa13 000110xxx 64/32 060000h?06ffffh 30000h?37fffh sa32 011001xxx 64/32 190000h?19ffffh c8000h?cffffh sa14 000111xxx 64/32 070000h?07ffffh 38000h?3ffffh sa33 011010xxx 64/32 1a0000h?1affffh d0000h?d7fffh sa15 001000xxx 64/32 080000h?08ffffh 40000h?47fffh sa34 011011xxx 64/32 1b0000h?1bffffh d8000h?dffffh sa16 001001xxx 64/32 090000h?09ffffh 48000h?4ffffh sa35 011000xxx 64/32 1c0000h?1cffffh e0000h?e7fffh sa17 001010xxx 64/32 0a0000h?0affffh 50000h?57fffh sa36 011101xxx 64/32 1d0000h?1dffffh e8000h?effffh sa18 001011xxx 64/32 0b0000h?0bffffh 58000h?5ffffh sa37 011110xxx 64/32 1e0000h?1effffh f0000h?f7fffh sa38 011111xxx 64/32 1f0000h?1fffffh f8000h?fffffh
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 25 preliminary table 7. s29gl032a (models r1, r2, w1, w2) sector addresses sector a20-a15 sector size (kb/ kwords) 8-bit address range 16-bit address range sector a20-a15 sector size (kb/ kwords) 8-bit address range 16-bit address range sa0 000000 64/32 000000?00ffff 000000?007fff sa32 1 00000 64/32 20 0000?20ffff 100000?107fff sa1 000001 64/32 010000?01ffff 008000?00ffff sa33 1 00001 64/32 21 0000?21ffff 108000?10ffff sa2 000010 64/32 020000?02ffff 010000?017fff sa34 1 00010 64/32 22 0000?22ffff 110000?117fff sa3 000011 64/32 030000?03ffff 018000?01ffff sa35 1 00011 64/32 23 0000?23ffff 118000?11ffff sa4 000100 64/32 040000?04ffff 020000?027fff sa36 1 00100 64/32 24 0000?24ffff 120000?127fff sa5 000101 64/32 050000?05ffff 028000?02ffff sa37 1 00101 64/32 25 0000?25ffff 128000?12ffff sa6 000110 64/32 060000?06ffff 030000?037fff sa38 1 00110 64/32 26 0000?26ffff 130000?137fff sa7 000111 64/32 070000?07ffff 038000?03ffff sa39 1 00111 64/32 27 0000?27ffff 138000?13ffff sa8 001000 64/32 080000?08ffff 040000?047fff sa40 1 01000 64/32 28 0000?28ffff 140000?147fff sa9 001001 64/32 090000?09ffff 048000?04ffff sa41 1 01001 64/32 29 0000?29ffff 148000?14ffff sa10 001010 64/32 0a 0000?0affff 050000?057fff sa42 1 01010 64/32 2a 0000?2affff 150000?157fff sa11 001011 64/32 0b 0000?0bffff 058000?05ffff sa43 1 01011 64/32 2b 0000?2bffff 158000?15ffff sa12 001100 64/32 0c 0000?0cffff 060000?067fff sa44 1 01100 64/32 2c 0000?2cffff 160000?167fff sa13 001101 64/32 0d 0000?0dffff 068000?06ffff sa45 1 01101 64/32 2d 0000?2dffff 168000?16ffff sa14 001110 64/32 0e 0000?0effff 070000?077fff sa46 1 01110 64/32 2e 0000?2effff 170000?177fff sa15 001111 64/32 0f 0000?0fffff 078000?07ffff sa47 1 01111 64/32 2f 0000?2fffff 178000?17ffff sa16 010000 64/32 100000?10ffff 080000?087fff sa48 1 10000 64/32 30 0000?30ffff 180000?187fff sa17 010001 64/32 110000?11ffff 088000?08ffff sa49 1 10001 64/32 31 0000?31ffff 188000?18ffff sa18 010010 64/32 120000?12ffff 090000?097fff sa50 1 10010 64/32 32 0000?32ffff 190000?197fff sa19 010011 64/32 130000?13ffff 098000?09ffff sa51 1 10011 64/32 33 0000?33ffff 198000?19ffff sa20 010100 64/32 140000?14ffff 0a0000?0a7fff sa52 1 10100 64/32 34 0000?34ffff 1a0000?1a7fff sa21 010101 64/32 150000?15ffff 0a8000?0affff sa53 1 10101 64/32 35 0000?35ffff 1a8000?1affff sa22 010110 64/32 160000?16ffff 0b0000?0b7fff sa54 1 10110 64/32 36 0000?36ffff 1b0000?1b7fff sa23 010111 64/32 170000?17ffff 0b8000?0bffff sa55 1 10111 64/32 37 0000?37ffff 1b8000?1bffff sa24 011000 64/32 180000?18ffff 0c0000?0c7fff sa56 1 11000 64/32 38 0000?38ffff 1c0000?1c7fff sa25 011001 64/32 190000?19ffff 0c8000?0cffff sa57 1 11001 64/32 39 0000?39ffff 1c8000?1cffff sa26 011010 64/32 1a 0000?1affff 0d0000?0d7fff sa58 1 11010 64/32 3a 0000?3affff 1d0000?1d7fff sa27 011011 64/32 1b 0000?1bffff 0d8000?0dffff sa59 1 11011 64/32 3b 0000?3bffff 1d8000?1dffff sa28 011100 64/32 1c 0000?1cffff 0e0000?0e7fff sa60 1 11100 64/32 3c 0000?3cffff 1e0000?1e7fff sa29 011101 64/32 1d 0000?1dffff 0e8000?0effff sa61 1 11101 64/32 3d 0000?3dffff 1e8000?1effff sa30 011110 64/32 1e 0000?1effff 0f0000?0f7fff sa62 1 11110 64/32 3e 0000?3effff 1f0000?1f7fff sa31 011111 64/32 1f 0000?1fffff 0f8000?0fffff sa63 1 11111 64/32 3f 0000?3fffff 1f8000?1fffff
26 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary table 8. s29gl032a (model r3, w3) top boot sector addresses sector a20?a12 sector size (kb/ kwords) 8-bit address range 16-bit address range sector a20?a12 sector size (kb/ kwords) 8-bit address range 16-bit address range sa0 000000xxx 64/32 000000h?00ffffh 00000h?07fffh sa36 100100xxx 64/32 240000h?24ffffh 120000h?127fffh sa1 000001xxx 64/32 010000h?01ffffh 08000h?0ffffh sa37 100101xxx 64/32 250000h?25ffffh 128000h?12ffffh sa2 000010xxx 64/32 020000h?02ffffh 10000h?17fffh sa38 100110xxx 64/32 260000h?26ffffh 130000h?137fffh sa3 000011xxx 64/32 030000h?03ffffh 18000h?1ffffh sa39 100111xxx 64/32 270000h?27ffffh 138000h?13ffffh sa4 000100xxx 64/32 040000h?04ffffh 20000h?27fffh sa40 101000xxx 64/32 280000h?28ffffh 140000h?147fffh sa5 000101xxx 64/32 050000h?05ffffh 28000h?2ffffh sa41 101001xxx 64/32 290000h?29ffffh 148000h?14ffffh sa6 000110xxx 64/32 060000h?06ffffh 30000h?37fffh sa42 101010xxx 64/32 2a0000h?2affffh 150000h?157fffh sa7 000111xxx 64/32 070000h?07ffffh 38000h?3ffffh sa43 101011xxx 64/32 2b0000h?2bffffh 158000h?15ffffh sa8 001000xxx 64/32 080000h?08ffffh 40000h?47fffh sa44 101100xxx 64/32 2c0000h?2cffffh 160000h?167fffh sa9 001001xxx 64/32 090000h?09ffffh 48000h?4ffffh sa45 101101xxx 64/32 2d0000h?2dffffh 168000h?16ffffh sa10 001010xxx 64/32 0a0000h?0affffh 50000h?57fffh sa46 101110xxx 64/32 2e0000h?2effffh 170000h?177fffh sa11 001011xxx 64/32 0b0000h?0bffffh 58000h?5ffffh sa47 101111xxx 64/32 2f0000h?2fffffh 178000h?17ffffh sa12 001100xxx 64/32 0c0000h?0cffffh 60000h?67fffh sa48 110000xxx 64/32 300000h?30ffffh 180000h?187fffh sa13 001101xxx 64/32 0d0000h?0dffffh 68000h?6ffffh sa49 110001xxx 64/32 310000h?31ffffh 188000h?18ffffh sa14 001101xxx 64/32 0e0000h?0effffh 70000h?77fffh sa50 110010xxx 64/32 320000h?32ffffh 190000h?197fffh sa15 001111xxx 64/32 0f0000h?0fffffh 78000h?7ffffh sa51 110011xxx 64/32 330000h?33ffffh 198000h?19ffffh sa16 010000xxx 64/32 100000h?00ffffh 80000h?87fffh sa52 100100xxx 64/32 340000h?34ffffh 1a0000h?1a7fffh sa17 010001xxx 64/32 110000h?11ffffh 88000h?8ffffh sa53 110101xxx 64/32 350000h?35ffffh 1a8000h?1affffh sa18 010010xxx 64/32 120000h?12ffffh 90000h?97fffh sa54 110110xxx 64/32 360000h?36ffffh 1b0000h?1b7fffh sa19 010011xxx 64/32 130000h?13ffffh 98000h?9ffffh sa55 110111xxx 64/32 370000h?37ffffh 1b8000h?1bffffh sa20 010100xxx 64/32 140000h?14ffffh a0000h?a7fffh sa56 111000xxx 64/32 380000h?38ffffh 1c0000h?1c7fffh sa21 010101xxx 64/32 150000h?15ffffh a8000h?affffh sa57 111001xxx 64/32 390000h?39ffffh 1c8000h?1cffffh sa22 010110xxx 64/32 160000h?16ffffh b0000h?b7fffh sa58 111010xxx 64/32 3a0000h?3affffh 1d0000h?1d7fffh sa23 010111xxx 64/32 170000h?17ffffh b8000h?bffffh sa59 111011xxx 64/32 3b0000h?3bffffh 1d8000h?1dffffh sa24 011000xxx 64/32 180000h?18ffffh c0000h?c7fffh sa60 111100xxx 64/32 3c0000h?3cffffh 1e0000h?1e7fffh sa25 011001xxx 64/32 190000h?19ffffh c8000h?cffffh sa61 111101xxx 64/32 3d0000h?3dffffh 1e8000h?1effffh sa26 011010xxx 64/32 1a0000h?1affffh d0000h?d7fffh sa 62 111110xxx 64/32 3e0000h?3effffh 1f0000h?1f7fffh sa27 011011xxx 64/32 1b0000h?1bffffh d8000h?dffffh sa63 111111000 8/4 3f0000h?3f1fffh 1f8000h?1f8fffh sa28 011100xxx 64/32 1c0000h?1cffffh e0000h?e7fffh sa64 111111001 8/4 3f2000h?3f3fffh 1f9000h?1f9fffh sa29 011101xxx 64/32 1d0000h?1dffffh e8000h?effffh sa65 111111010 8/4 3f4000h?3f5fffh 1fa000h?1fafffh sa30 011110xxx 64/32 1e0000h?1effffh f0000h?f7fffh sa66 111111011 8/4 3f6000h?3f7fffh 1fb000h?1fbfffh sa31 011111xxx 64/32 1f0000h?1fffffh f8000h?fffffh sa67 111111100 8/4 3f8000h?3f9fffh 1fc000h?1fcfffh sa32 100000xxx 64/32 200000h?20ffffh f9000h?107fffh sa68 111111101 8/4 3fa000h?3fbfffh 1fd000h?1fdfffh sa33 100001xxx 64/32 210000h?21ffffh 108000h?10ffffh sa69 111111110 8/4 3fc000h?3fdfffh 1fe000h?1fefffh sa34 100010xxx 64/32 220000h?22ffffh 110000h?117fffh sa70 111111111 8/4 3fe000h?3fffffh 1ff000h?1fffffh sa35 101011xxx 64/32 230000h?23ffffh 118000h?11ffffh
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 27 preliminary ta b l e 9 . s29gl032a (model r4, w4) bottom boot sector addresses sector a20?a12 sector size (kb/ kwords) 8-bit address range 16-bit address range sector a20?a12 sector size (kb/ kwords) 8-bit address range 16-bit address range sa0 000000000 8/4 000000h?001fffh 00000h?00fffh sa19 001100xxx 64/32 0c0000h?0cffffh 60000h?67fffh sa1 000000001 8/4 002000h?003fffh 01000h?01fffh sa20 001101xxx 64/32 0d0000h?0dffffh 68000h?6ffffh sa2 000000010 8/4 004000h?005fffh 02000h?02fffh sa21 001101xxx 64/32 0e0000h?0effffh 70000h?77fffh sa3 000000011 8/4 006000h?007fffh 03000h?03fffh sa22 001111xxx 64/32 0f0000h?0fffffh 78000h?7ffffh sa4 000000100 8/4 008000h?009fffh 04000h?04fffh sa23 010000xxx 64/32 100000h?00ffffh 80000h?87fffh sa5 000000101 8/4 00a000h?00bfffh 05000h?05fffh sa24 010001xxx 64/32 110000h?11ffffh 88000h?8ffffh sa6 000000110 8/4 00c000h?00dfffh 06000h?06fffh sa25 010010xxx 64/32 120000h?12ffffh 90000h?97fffh sa7 000000111 8/4 00e000h?00fffffh 07000h?07fffh sa26 010011xxx 64/32 130000h?13ffffh 98000h?9ffffh sa8 000001xxx 64/32 010000h?01ffffh 08000h?0ffffh sa27 010100xxx 64/32 140000h?14ffffh a0000h?a7fffh sa9 000010xxx 64/32 020000h?02ffffh 10000h?17fffh sa28 010101xxx 64/32 150000h?15ffffh a8000h?affffh sa10 000011xxx 64/32 030000h?03ffffh 18000h?1ffffh sa29 010110xxx 64/32 160000h?16ffffh b0000h?b7fffh sa11 000100xxx 64/32 040000h?04ffffh 20000h?27fffh sa30 010111xxx 64/32 170000h?17ffffh b8000h?bffffh sa12 000101xxx 64/32 050000h?05ffffh 28000h?2ffffh sa31 011000xxx 64/32 180000h?18ffffh c0000h?c7fffh sa13 000110xxx 64/32 060000h?06ffffh 30000h?37fffh sa32 011001xxx 64/32 190000h?19ffffh c8000h?cffffh sa14 000111xxx 64/32 070000h?07ffffh 38000h?3ffffh sa33 011010xxx 64/32 1a0000h?1affffh d0000h?d7fffh sa15 001000xxx 64/32 080000h?08ffffh 40000h?47fffh sa34 011011xxx 64/32 1b0000h?1bffffh d8000h?dffffh sa16 001001xxx 64/32 090000h?09ffffh 48000h?4ffffh sa35 011000xxx 64/32 1c0000h?1cffffh e0000h?e7fffh sa17 001010xxx 64/32 0a0000h?0affffh 50000h?57fffh sa36 011101xxx 64/32 1d0000h?1dffffh e8000h?effffh sa18 001011xxx 64/32 0b0000h?0bffffh 58000h?5ffffh sa37 011110xxx 64/32 1e0000h?1effffh f0000h?f7fffh sa38 011111xxx 64/32 1f0000h?1fffffh f8000h?fffffh sa55 110000xxx 64/32 300000h?30ffffh 180000h?187fffh sa39 100000xxx 64/32 200000h?20ffffh f9000h?107fffh sa56 110001xxx 64/32 310000h?31ffffh 188000h?18ffffh sa40 100001xxx 64/32 210000h?21ffffh 108000h?10ffffh sa57 110010xxx 64/32 320000h?32ffffh 190000h?197fffh sa41 100010xxx 64/32 220000h?22ffffh 110000h?117fffh sa58 110011xxx 64/32 330000h?33ffffh 198000h?19ffffh sa42 101011xxx 64/32 230000h?23ffffh 118000h?11ffffh sa59 100100xxx 64/32 340000h?34ffffh 1a0000h?1a7fffh sa43 100100xxx 64/32 240000h?24ffffh 120000h?127fffh sa60 110101xxx 64/32 350000h?35ffffh 1a8000h?1affffh sa44 100101xxx 64/32 250000h?25ffffh 128000h?12ffffh sa61 110110xxx 64/32 360000h?36ffffh 1b0000h?1b7fffh sa45 100110xxx 64/32 260000h?26ffffh 130000h?137fffh sa62 110111xxx 64/32 370000h?37ffffh 1b8000h?1bffffh sa46 100111xxx 64/32 270000h?27ffffh 138000h?13ffffh sa63 111000xxx 64/32 380000h?38ffffh 1c0000h?1c7fffh sa47 101000xxx 64/32 280000h?28ffffh 140000h?147fffh sa64 111001xxx 64/32 390000h?39ffffh 1c8000h?1cffffh sa48 101001xxx 64/32 290000h?29ffffh 148000h?14ffffh sa65 111010xxx 64/32 3a0000h?3affffh 1d0000h?1d7fffh sa49 101010xxx 64/32 2a0000h?2affffh 150000h?157fffh sa66 111011xxx 64/32 3b0000h?3bffffh 1d8000h?1dffffh sa50 101011xxx 64/32 2b0000h?2bffffh 158000h?15ffffh sa67 111100xxx 64/32 3c0000h?3cffffh 1e0000h?1e7fffh sa51 101100xxx 64/32 2c0000h?2cffffh 160000h?167fffh sa68 111101xxx 64/32 3d0000h?3dffffh 1e8000h?1effffh sa52 101101xxx 64/32 2d0000h?2dffffh 168000h?16ffffh sa69 111110xxx 64/32 3e0000h?3effffh 1f0000h?1f7fffh sa53 101110xxx 64/32 2e0000h?2effffh 170000h?177fffh sa70 111111xxx 64/32 3f0000h?3fffffh 1f8000h?1fffffh sa54 101111xxx 64/32 2f0000h?2fffffh 178000h?17ffffh
28 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary ta b l e 1 0 . s29gl064a (models r1, r2, r8, r9, w1, w2) sector addresses (sheet 1 of 2) sector a21?a15 sector size (kb/ kwords) 8-bit address range 16-bit address range sector a21?a15 sector size (kb/ kwords) 8-bit address range 16-bit address range sa0 0000000 64/32 000000?00ffff 000000?007fff sa37 0100101 64/32 250000?25ffff 128000?12ffff sa1 0000001 64/32 010000?01ffff 008000?00ffff sa38 0100110 64/32 260000?26ffff 130000?137fff sa2 0000010 64/32 020000?02ffff 010000?017fff sa39 0100111 64/32 270000?27ffff 138000?13ffff sa3 0000011 64/32 030000?03ffff 018000?01ffff sa40 0101000 64/32 280000?28ffff 140000?147fff sa4 0000100 64/32 040000?04ffff 020000?027fff sa41 0101001 64/32 290000?29ffff 148000?14ffff sa5 0000101 64/32 050000?05ffff 028000?02ffff sa42 0101010 64/32 2a0000?2affff 150000?157fff sa6 0000110 64/32 060000?06ffff 030000?037fff sa43 0101011 64/32 2b0000?2bffff 158000?15ffff sa7 0000111 64/32 070000?07ffff 038000?03ffff sa44 0101100 64/32 2c0000?2cffff 160000?167fff sa8 0001000 64/32 080000?08ffff 040000?047fff sa45 0101101 64/32 2d0000?2dffff 168000?16ffff sa9 0001001 64/32 090000?09ffff 048000?04ffff sa46 0101110 64/32 2e0000?2effff 170000?177fff sa10 0001010 64/32 0a0000?0affff 050000?057fff sa47 0101111 64/32 2f0000?2fffff 178000?17ffff sa11 0001011 64/32 0b0000?0bffff 058000?05ffff sa48 0110000 64/32 300000?30ffff 180000?187fff sa12 0001100 64/32 0c0000?0cffff 060000?067fff sa49 0110001 64/32 310000?31ffff 188000?18ffff sa13 0001101 64/32 0d0000?0dffff 068000?06ffff sa50 0110010 64/32 320000?32ffff 190000?197fff sa14 0001110 64/32 0e0000?0effff 070000?077fff sa51 0110011 64/32 330000?33ffff 198000?19ffff sa15 0001111 64/32 0f0000?0fffff 078000?07ffff sa52 0110100 64/32 340000?34ffff 1a0000?1a7fff sa16 0010000 64/32 100000?10ffff 080000?087fff sa53 0110101 64/32 350000?35ffff 1a8000?1affff sa17 0010001 64/32 110000?11ffff 088000?08ffff sa54 0110110 64/32 360000?36ffff 1b0000?1b7fff sa18 0010010 64/32 120000?12ffff 090000?097fff sa55 0110111 64/32 370000?37ffff 1b8000?1bffff sa19 0010011 64/32 130000?13ffff 098000?09ffff sa56 0111000 64/32 380000?38ffff 1c0000?1c7fff sa20 0010100 64/32 140000?14ffff 0a0000?0a7fff sa57 0111001 64/32 390000?39ffff 1c8000?1cffff sa21 0010101 64/32 150000?15ffff 0a8000?0affff sa58 0111010 64/32 3a0000?3affff 1d0000?1d7fff sa22 0010110 64/32 160000?16ffff 0b0000?0b7fff sa59 0111011 64/32 3b0000?3bffff 1d8000?1dffff sa23 0010111 64/32 170000?17ffff 0b8000?0bffff sa60 0111100 64/32 3c0000?3cffff 1e0000?1e7fff sa24 0011000 64/32 180000?18ffff 0c0000?0c7fff sa61 0111101 64/32 3d0000?3dffff 1e8000?1effff sa25 0011001 64/32 190000?19ffff 0c8000?0cffff sa62 0111110 64/32 3e0000?3effff 1f0000?1f7fff sa26 0011010 64/32 1a0000?1affff 0d0000?0d7fff sa63 0111111 64/32 3f0000?3fffff 1f8000?1fffff sa27 0011011 64/32 1b0000?1bffff 0d8000?0dffff sa64 1000000 64/32 400000?40ffff 200000?207fff sa28 0011100 64/32 1c0000?1cffff 0e0000?0e7fff sa65 1000001 64/32 410000?41ffff 208000?20ffff sa29 0011101 64/32 1d0000?1dffff 0e8000?0effff sa66 1000010 64/32 420000?42ffff 210000?217fff sa30 0011110 64/32 1e0000?1effff 0f0000?0f7fff sa67 1000011 64/32 430000?43ffff 218000?21ffff sa31 0011111 64/32 1f0000?1fffff 0f8000?0fffff sa68 1000100 64/32 440000?44ffff 220000?227fff sa32 0100000 64/32 200000?20ffff 100000?107fff sa69 1000101 64/32 450000?45ffff 228000?22ffff sa33 0100001 64/32 210000?21ffff 108000?10ffff sa70 1000110 64/32 460000?46ffff 230000?237fff sa34 0100010 64/32 220000?22ffff 110000?117fff sa71 1000111 64/32 470000?47ffff 238000?23ffff sa35 0100011 64/32 230000?23ffff 118000?11ffff sa72 1001000 64/32 480000?48ffff 240000?247fff sa36 0100100 64/32 240000?24ffff 120000?127fff sa73 1001001 64/32 490000?49ffff 248000?24ffff
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 29 preliminary sa74 1001010 64/32 4a0000?4affff 250000?257fff sa101 1100101 64/32 650000?65ffff 328000?32ffff sa75 1001011 64/32 4b0000?4bffff 258000?25ffff sa102 1100110 64/32 660000?66ffff 330000?337fff sa76 1001100 64/32 4c0000?4cffff 260000?267fff sa103 1100111 64/32 670000?67ffff 338000?33ffff sa77 1001101 64/32 4d0000?4dffff 268000?26ffff sa104 1101000 64/32 680000?68ffff 340000?347fff sa78 1001110 64/32 4e0000?4effff 270000?277fff sa105 1101001 64/32 690000?69ffff 348000?34ffff sa79 1001111 64/32 4f0000?4fffff 278000?27ffff sa106 1101010 64/32 6a0000?6affff 350000?357fff sa80 1010000 64/32 500000?50ffff 280000?287fff sa107 1101011 64/32 6b0000?6bffff 358000?35ffff sa81 1010001 64/32 510000?51ffff 288000?28ffff sa108 1101100 64/32 6c0000?6cffff 360000?367fff sa82 1010010 64/32 520000?52ffff 290000?297fff sa109 1101101 64/32 6d0000?6dffff 368000?36ffff sa83 1010011 64/32 530000?53ffff 298000?29ffff sa110 1101110 64/32 6e0000?6effff 370000?377fff sa84 1010100 64/32 540000?54ffff 2a0000?2a7fff sa111 1101111 64/32 6f0000?6fffff 378000?37ffff sa85 1010101 64/32 550000?55ffff 2a8000?2affff sa112 1110000 64/32 700000?70ffff 380000?387fff sa86 1010110 64/32 560000?56ffff 2b0000?2b7fff sa113 1110001 64/32 710000?71ffff 388000?38ffff sa87 1010111 64/32 570000?57ffff 2b8000?2bffff sa114 1110010 64/32 720000?72ffff 390000?397fff sa88 1011000 64/32 580000?58ffff 2c0000?2c7fff sa115 1110011 64/32 730000?73ffff 398000?39ffff sa89 1011001 64/32 590000?59ffff 2c8000?2cffff sa116 1110100 64/32 740000?74ffff 3a0000?3a7fff sa90 1011010 64/32 5a0000?5affff 2d0000?2d7fff sa117 1110101 64/32 750000?75ffff 3a8000?3affff sa91 1011011 64/32 5b0000?5bffff 2d8000?2dffff sa118 1110110 64/32 760000?76ffff 3b0000?3b7fff sa92 1011100 64/32 5c0000?5cffff 2e0000?2e7fff sa119 1110111 64/32 770000?77ffff 3b8000?3bffff sa93 1011101 64/32 5d0000?5dffff 2e8000?2effff sa120 1111000 64/32 780000?78ffff 3c0000?3c7fff sa94 1011110 64/32 5e0000?5effff 2f0000?2f7fff sa121 1111001 64/32 790000?79ffff 3c8000?3cffff sa95 1011111 64/32 5f0000?5fffff 2f8000?2fffff sa122 1111010 64/32 7a0000?7affff 3d0000?3d7fff sa96 1100000 64/32 600000?60ffff 300000?307fff sa123 1111011 64/32 7b0000?7bffff 3d8000?3dffff sa97 1100001 64/32 610000?61ffff 308000?30ffff sa124 1111100 64/32 7c0000?7cffff 3e0000?3e7fff sa98 1100010 64/32 620000?62ffff 310000?317fff sa125 1111101 64/32 7d0000?7dffff 3e8000?3effff sa99 1100011 64/32 630000?63ffff 318000?31ffff sa126 1111110 64/32 7e0000?7effff 3f0000?3f7fff sa100 1100100 64/32 640000?64ffff 320000?327fff sa127 1111111 64/32 7f0000?7fffff 3f8000?3fffff table 10. s29gl064a (models r1, r2, r8, r9, w1, w2) sector addresses (sheet 2 of 2) sector a21?a15 sector size (kb/ kwords) 8-bit address range 16-bit address range sector a21?a15 sector size (kb/ kwords) 8-bit address range 16-bit address range
30 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary table 11. s29gl064a (model r3, w3) top boot sector addresses (sheet 1 of 2) sector a21?a12 sector size (kb/ kwords) 8-bit address range 16-bit address range sector a21?a12 sector size (kb/ kwords) 8-bit address range 16-bit address range sa0 0000000xxx 64/32 000000h?00ffffh 00000h?07fffh sa34 0100010xxx 64/32 220000h?22ffffh 110000h?117fffh sa1 0000001xxx 64/32 010000h?01ffffh 08000h?0ffffh sa35 0101011xxx 64/32 230000h?23ffffh 118000h?11ffffh sa2 0000010xxx 64/32 020000h?02ffffh 10000h?17fffh sa36 0100100xxx 64/32 240000h?24ffffh 120000h?127fffh sa3 0000011xxx 64/32 030000h?03ffffh 18000h?1ffffh sa37 0100101xxx 64/32 250000h?25ffffh 128000h?12ffffh sa4 0000100xxx 64/32 040000h?04ffffh 20000h?27fffh sa38 0100110xxx 64/32 260000h?26ffffh 130000h?137fffh sa5 0000101xxx 64/32 050000h?05ffffh 28000h?2ffffh sa39 0100111xxx 64/32 270000h?27ffffh 138000h?13ffffh sa6 0000110xxx 64/32 060000h?06ffffh 30000h?37fffh sa40 0101000xxx 64/32 280000h?28ffffh 140000h?147fffh sa7 0000111xxx 64/32 070000h?07ffffh 38000h?3ffffh sa41 0101001xxx 64/32 290000h?29ffffh 148000h?14ffffh sa8 0001000xxx 64/32 080000h?08ffffh 40000h?47fffh sa42 0101010xxx 64/32 2a0000h?2affffh 150000h?157fffh sa9 0001001xxx 64/32 090000h?09ffffh 48000h?4ffffh sa43 0101011xxx 64/32 2b0000h?2bffffh 158000h?15ffffh sa10 0001010xxx 64/32 0a0000h?0affffh 50000h?57fffh sa44 0101100xxx 64/32 2c0000h?2cffffh 160000h?167fffh sa11 0001011xxx 64/32 0b0000h?0bffffh 58000h?5ffffh sa45 0101101xxx 64/32 2d0000h?2dffffh 168000h?16ffffh sa12 0001100xxx 64/32 0c0000h?0cffffh 60000h?67fffh sa46 0101110xxx 64/32 2e0000h?2effffh 170000h?177fffh sa13 0001101xxx 64/32 0d0000h?0dffffh 68000h?6ffffh sa47 0101111xxx 64/32 2f0000h?2fffffh 178000h?17ffffh sa14 0001101xxx 64/32 0e0000h?0effffh 70000h?77fffh sa48 0110000xxx 64/32 300000h?30ffffh 180000h?187fffh sa15 0001111xxx 64/32 0f0000h?0fffffh 78000h?7ffffh sa49 0110001xxx 64/32 310000h?31ffffh 188000h?18ffffh sa16 0010000xxx 64/32 100000h?00ffffh 80000h?87fffh sa50 0110010xxx 64/32 320000h?32ffffh 190000h?197fffh sa17 0010001xxx 64/32 110000h?11ffffh 88000h?8ffffh sa51 0110011xxx 64/32 330000h?33ffffh 198000h?19ffffh sa18 0010010xxx 64/32 120000h?12ffffh 90000h?97fffh sa52 0100100xxx 64/32 340000h?34ffffh 1a0000h?1a7fffh sa19 0010011xxx 64/32 130000h?13ffffh 98000h?9ffffh sa53 0110101xxx 64/32 350000h?35ffffh 1a8000h?1affffh sa20 0010100xxx 64/32 140000h?14ffffh a0000h?a7fffh sa54 0110110xxx 64/32 360000h?36ffffh 1b0000h?1b7fffh sa21 0010101xxx 64/32 150000h?15ffffh a8000h?affffh sa55 0110111xxx 64/32 370000h?37ffffh 1b8000h?1bffffh sa22 0010110xxx 64/32 160000h?16ffffh b0000h?b7fffh sa56 0111000xxx 64/32 380000h?38ffffh 1c0000h?1c7fffh sa23 0010111xxx 64/32 170000h?17ffffh b8000h?bffffh sa57 0111001xxx 64/32 390000h?39ffffh 1c8000h?1cffffh sa24 0011000xxx 64/32 180000h?18ffffh c0000h?c7fffh sa58 0111010xxx 64/32 3a0000h?3affffh 1d0000h?1d7fffh sa25 0011001xxx 64/32 190000h?19ffffh c8000h?cffffh sa59 0111011xxx 64/32 3b0000h?3bffffh 1d8000h?1dffffh sa26 0011010xxx 64/32 1a0000h?1affffh d0000h?d7fffh sa60 0111100xxx 64/32 3c0000h?3cffffh 1e0000h?1e7fffh sa27 0011011xxx 64/32 1b0000h?1bffffh d8000h?dffffh sa61 0111101xxx 64/32 3d0000h?3dffffh 1e8000h?1effffh sa28 0011000xxx 64/32 1c0000h?1cffffh e0000h?e7fffh sa62 0111110xxx 64/32 3e0000h?3effffh 1f0000h?1f7fffh sa29 0011101xxx 64/32 1d0000h?1dffffh e8000h?effffh sa63 0111111xxx 64/32 3f0000h?3fffffh 1f8000h?1fffffh sa30 0011110xxx 64/32 1e0000h?1effffh f0000h?f7fffh sa64 1000000xxx 64/32 400000h?40ffffh 200000h?207fffh sa31 0011111xxx 64/32 1f0000h?1fffffh f8000h?fffffh sa65 1000001xxx 64/32 410000h?41ffffh 208000h?20ffffh sa32 0100000xxx 64/32 200000h?20ffffh f9000h?107fffh sa66 1000010xxx 64/32 420000h?42ffffh 210000h?217fffh sa33 0100001xxx 64/32 210000h?21ffffh 108000h?10ffffh sa67 1000011xxx 64/32 430000h?43ffffh 218000h?21ffffh sa68 1000100xxx 64/32 440000h?44ffffh 220000h?227fffh sa102 1100110xxx 64/32 660000h?66ffffh 330000h?337fffh sa69 1000101xxx 64/32 450000h?45ffffh 228000h?22ffffh sa103 1100111xxx 64/32 670000h?67ffffh 338000h?33ffffh sa70 1000110xxx 64/32 460000h?46ffffh 230000h?237fffh sa104 1101000xxx 64/32 680000h?68ffffh 340000h?347fffh sa71 1000111xxx 64/32 470000h?47ffffh 238000h?23ffffh sa105 1101001xxx 64/32 690000h?69ffffh 348000h?34ffffh sa72 1001000xxx 64/32 480000h?48ffffh 240000h?247fffh sa106 1101010xxx 64/32 6a0000h?6affffh 350000h?357fffh sa73 1001001xxx 64/32 490000h?49ffffh 248000h?24ffffh sa107 1101011xxx 64/32 6b0000h?6bffffh 358000h?35ffffh sa74 1001010xxx 64/32 4a0000h?4affffh 250000h?257fffh sa108 1101100xxx 64/32 6c0000h?6cffffh 360000h?367fffh
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 31 preliminary sa75 1001011xxx 64/32 4b0000h?4bffffh 258000h?25ffffh sa109 1101101xxx 64/32 6d0000h?6dffffh 368000h?36ffffh sa76 1001100xxx 64/32 4c0000h?4cffffh 260000h?267fffh sa110 1101110xxx 64/32 6e0000h?6effffh 370000h?377fffh sa77 1001101xxx 64/32 4d0000h?4dffffh 268000h?26ffffh sa111 1101111xxx 64/32 6f0000h?6fffffh 378000h?37ffffh sa78 1001110xxx 64/32 4e0000h?4effffh 270000h?277fffh sa112 1110000xxx 64/32 700000h?70ffffh 380000h?387fffh sa79 1001111xxx 64/32 4f0000h?4fffffh 278000h?27ffffh sa113 1110001xxx 64/32 710000h?71ffffh 388000h?38ffffh sa80 1010000xxx 64/32 500000h?50ffffh 280000h?28ffffh sa114 1110010xxx 64/32 720000h?72ffffh 390000h?397fffh sa81 1010001xxx 64/32 510000h?51ffffh 288000h?28ffffh sa115 1110011xxx 64/32 730000h?73ffffh 398000h?39ffffh sa82 1010010xxx 64/32 520000h?52ffffh 290000h?297fffh sa116 1110100xxx 64/32 740000h?74ffffh 3a0000h?3a7fffh sa83 1010011xxx 64/32 530000h?53ffffh 298000h?29ffffh sa117 1110101xxx 64/32 750000h?75ffffh 3a8000h?3affffh sa84 1010100xxx 64/32 540000h?54ffffh 2a0000h?2a7fffh sa118 1110110xxx 64/32 760000h?76ffffh 3b0000h?3b7fffh sa85 1010101xxx 64/32 550000h?55ffffh 2a8000h?2affffh sa119 1110111xxx 64/32 770000h?77ffffh 3b8000h?3bffffh sa86 1010110xxx 64/32 560000h?56ffffh 2b0000h?2b7fffh sa120 1111000xxx 64/32 780000h?78ffffh 3c0000h?3c7fffh sa87 1010111xxx 64/32 570000h?57ffffh 2b8000h?2bffffh sa121 1111001xxx 64/32 790000h?79ffffh 3c8000h?3cffffh sa88 1011000xxx 64/32 580000h?58ffffh 2c0000h?2c7fffh sa122 1111010xxx 64/32 7a0000h?7affffh 3d0000h?3d7fffh sa89 1011001xxx 64/32 590000h?59ffffh 2c8000h?2cffffh sa123 1111011xxx 64/32 7b0000h?7bffffh 3d8000h?3dffffh sa90 1011010xxx 64/32 5a0000h?5affffh 2d0000h?2d7fffh sa124 1111100xxx 64/32 7c0000h?7cffffh 3e0000h?3e7fffh sa91 1011011xxx 64/32 5b0000h?5bffffh 2d8000h?2dffffh sa125 1111101xxx 64/32 7d0000h?7dffffh 3e8000h?3effffh sa92 1011100xxx 64/32 5c0000h?5cffffh 2e0000h?2e7fffh sa126 1111110xxx 64/32 7e0000h?7effffh 3f0000h?3f7fffh sa93 1011101xxx 64/32 5d0000h?5dffffh 2e8000h?2effffh sa127 1111111000 8/4 7f0000h?7f1fffh 3f8000h?3f8fffh sa94 1011110xxx 64/32 5e0000h?5effffh 2f0000h?2fffffh sa128 1111111001 8/4 7f2000h?7f3fffh 3f9000h?3f9fffh sa95 1011111xxx 64/32 5f0000h?5fffffh 2f8000h?2fffffh sa129 1111111010 8/4 7f4000h?7f5fffh 3fa000h?3fafffh sa96 1100000xxx 64/32 600000h?60ffffh 300000h?307fffh sa130 1111111011 8/4 7f6000h?7f7fffh 3fb000h?3fbfffh sa97 1100001xxx 64/32 610000h?61ffffh 308000h?30ffffh sa131 1111111100 8/4 7f8000h?7f9fffh 3fc000h?3fcfffh sa98 1100010xxx 64/32 620000h?62ffffh 310000h?317fffh sa132 1111111101 8/4 7fa000h?7fbfffh 3fd000h?3fdfffh sa99 1100011xxx 64/32 630000h?63ffffh 318000h?31ffffh sa133 1111111110 8/4 7fc000h?7fdfffh 3fe000h?3fefffh sa100 1100100xxx 64/32 640000h?64ffffh 320000h?327fffh sa134 1111111111 8/4 7fe000h?7fffffh 3ff000h?3fffffh sa101 1100101xxx 64/32 650000h?65ffffh 328000h?32ffffh table 11. s29gl064a (model r3, w3) top boot sector addresses (sheet 2 of 2) sector a21?a12 sector size (kb/ kwords) 8-bit address range 16-bit address range sector a21?a12 sector size (kb/ kwords) 8-bit address range 16-bit address range
32 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary ta b l e 1 2 . s29gl064a (model r4, w4) b ottom boot sector addresses (sheet 1 of 2) sector a21?a12 sector size (kb/ kwords) 8-bit address range 16-bit address range sector a21?a12 sector size (kb/ kwords) 8-bit address range 16-bit address range sa0 0000000000 8/4 000000h?001fffh 00000h?00fffh sa27 0010100xxx 64/32 140000h?14ffffh a0000h?a7fffh sa1 0000000001 8/4 002000h?003fffh 01000h?01fffh sa28 0010101xxx 64/32 150000h?15ffffh a8000h?affffh sa2 0000000010 8/4 004000h?005fffh 02000h?02fffh sa29 0010110xxx 64/32 160000h?16ffffh b0000h?b7fffh sa3 0000000011 8/4 006000h?007fffh 03000h?03fffh sa30 0010111xxx 64/32 170000h?17ffffh b8000h?bffffh sa4 0000000100 8/4 008000h?009fffh 04000h?04fffh sa31 0011000xxx 64/32 180000h?18ffffh c0000h?c7fffh sa5 0000000101 8/4 00a000h?00bfffh 05000h?05fffh sa32 0011001xxx 64/32 190000h?19ffffh c8000h?cffffh sa6 0000000110 8/4 00c000h?00dfffh 06000h?06fffh sa33 0011010xxx 64/32 1a0000h?1affffh d0000h?d7fffh sa7 0000000111 8/4 00e000h?00fffffh 07000h?07fffh sa34 0011011xxx 64/32 1b0000h?1bffffh d8000h?dffffh sa8 0000001xxx 64/32 010000h?01ffffh 08000h?0ffffh sa35 0011000xxx 64/32 1c0000h?1cffffh e0000h?e7fffh sa9 0000010xxx 64/32 020000h?02ffffh 10000h?17fffh sa36 0011101xxx 64/32 1d0000h?1dffffh e8000h?effffh sa10 0000011xxx 64/32 030000h?03ffffh 18000h?1ffffh sa37 0011110xxx 64/32 1e0000h?1effffh f0000h?f7fffh sa11 0000100xxx 64/32 040000h?04ffffh 20000h?27fffh sa38 0011111xxx 64/32 1f0000h?1fffffh f8000h?fffffh sa12 0000101xxx 64/32 050000h?05ffffh 28000h?2ffffh sa39 0100000xxx 64/32 200000h?20ffffh f9000h?107fffh sa13 0000110xxx 64/32 060000h?06ffffh 30000h?37fffh sa40 0100001xxx 64/32 210000h?21ffffh 108000h?10ffffh sa14 0000111xxx 64/32 070000h?07ffffh 38000h?3ffffh sa41 0100010xxx 64/32 220000h?22ffffh 110000h?117fffh sa15 0001000xxx 64/32 080000h?08ffffh 40000h?47fffh sa42 0101011xxx 64/32 230000h?23ffffh 118000h?11ffffh sa16 0001001xxx 64/32 090000h?09ffffh 48000h?4ffffh sa43 0100100xxx 64/32 240000h?24ffffh 120000h?127fffh sa17 0001010xxx 64/32 0a0000h?0affffh 50000h?57fffh sa44 0100101xxx 64/32 250000h?25ffffh 128000h?12ffffh sa18 0001011xxx 64/32 0b0000h?0bffffh 58000h?5ffffh sa45 0100110xxx 64/32 260000h?26ffffh 130000h?137fffh sa19 0001100xxx 64/32 0c0000h?0cffffh 60000h?67fffh sa46 0100111xxx 64/32 270000h?27ffffh 138000h?13ffffh sa20 0001101xxx 64/32 0d0000h?0dffffh 68000h?6ffffh sa47 0101000xxx 64/32 280000h?28ffffh 140000h?147fffh sa21 0001101xxx 64/32 0e0000h?0effffh 70000h?77fffh sa48 0101001xxx 64/32 290000h?29ffffh 148000h?14ffffh sa22 0001111xxx 64/32 0f0000h?0fffffh 78000h?7ffffh sa49 0101010xxx 64/32 2a0000h?2affffh 150000h?157fffh sa23 0010000xxx 64/32 100000h?00ffffh 80000h?87fffh sa50 0101011xxx 64/32 2b0000h?2bffffh 158000h?15ffffh sa24 0010001xxx 64/32 110000h?11ffffh 88000h?8ffffh sa51 0101100xxx 64/32 2c0000h?2cffffh 160000h?167fffh sa25 0010010xxx 64/32 120000h?12ffffh 90000h?97fffh sa52 0101101xxx 64/32 2d0000h?2dffffh 168000h?16ffffh sa26 0010011xxx 64/32 130000h?13ffffh 98000h?9ffffh sa53 0101110xxx 64/32 2e0000h?2effffh 170000h?177fffh sa54 0101111xxx 64/32 2f0000h?2fffffh 178000h?17ffffh sa95 1011000xxx 64/32 580000h?58ffffh 2c0000h?2c7fffh sa55 0110000xxx 64/32 300000h?30ffffh 180000h?187fffh sa96 1011001xxx 64/32 590000h?59ffffh 2c8000h?2cffffh sa56 0110001xxx 64/32 310000h?31ffffh 188000h?18ffffh sa97 1011010xxx 64/32 5a0000h?5affffh 2d0000h?2d7fffh sa57 0110010xxx 64/32 320000h?32ffffh 190000h?197fffh sa98 1011011xxx 64/32 5b0000h?5bffffh 2d8000h?2dffffh sa58 0110011xxx 64/32 330000h?33ffffh 198000h?19ffffh sa99 1011100xxx 64/32 5c0000h?5cffffh 2e0000h?2e7fffh sa59 0100100xxx 64/32 340000h?34ffffh 1a0000h?1a7fffh sa100 1011101xxx 64/32 5d0000h?5dffffh 2e8000h?2effffh sa60 0110101xxx 64/32 350000h?35ffffh 1a8000h?1affffh sa101 1011110xxx 64/32 5e0000h?5effffh 2f0000h?2fffffh sa61 0110110xxx 64/32 360000h?36ffffh 1b0000h?1b7fffh sa102 1011111xxx 64/32 5f0000h?5fffffh 2f8000h?2fffffh sa62 0110111xxx 64/32 370000h?37ffffh 1b8000h?1bffffh sa103 1100000xxx 64/32 600000h?60ffffh 300000h?307fffh sa63 0111000xxx 64/32 380000h?38ffffh 1c0000h?1c7fffh sa104 1100001xxx 64/32 610000h?61ffffh 308000h?30ffffh sa64 0111001xxx 64/32 390000h?39ffffh 1c8000h?1cffffh sa105 1100010xxx 64/32 620000h?62ffffh 310000h?317fffh sa65 0111010xxx 64/32 3a0000h?3affffh 1d0000h?1d7fffh sa106 1100011xxx 64/32 630000h?63ffffh 318000h?31ffffh sa66 0111011xxx 64/32 3b0000h?3bffffh 1d8000h?1dffffh sa107 1100100xxx 64/32 640000h?64ffffh 320000h?327fffh sa67 0111100xxx 64/32 3c0000h?3cffffh 1e0000h?1e7fffh sa108 1100101xxx 64/32 650000h?65ffffh 328000h?32ffffh sa68 0111101xxx 64/32 3d0000h?3dffffh 1e8000h?1effffh sa109 1100110xxx 64/32 660000h?66ffffh 330000h?337fffh sa69 0111110xxx 64/32 3e0000h?3effffh 1f0000h?1f7fffh sa110 1100111xxx 64/32 670000h?67ffffh 338000h?33ffffh
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 33 preliminary sa70 0111111xxx 64/32 3f0000h?3fffffh 1f8000h?1fffffh sa111 1101000xxx 64/32 680000h?68ffffh 340000h?347fffh sa71 1000000xxx 64/32 400000h?40ffffh 200000h?207fffh sa112 1101001xxx 64/32 690000h?69ffffh 348000h?34ffffh sa72 1000001xxx 64/32 410000h?41ffffh 208000h?20ffffh sa113 1101010xxx 64/32 6a0000h?6affffh 350000h?357fffh sa73 1000010xxx 64/32 420000h?42ffffh 210000h?217fffh sa114 1101011xxx 64/32 6b0000h?6bffffh 358000h?35ffffh sa74 1000011xxx 64/32 430000h?43ffffh 218000h?21ffffh sa115 1101100xxx 64/32 6c0000h?6cffffh 360000h?367fffh sa75 1000100xxx 64/32 440000h?44ffffh 220000h?227fffh sa116 1101101xxx 64/32 6d0000h?6dffffh 368000h?36ffffh sa76 1000101xxx 64/32 450000h?45ffffh 228000h?22ffffh sa117 1101110xxx 64/32 6e0000h?6effffh 370000h?377fffh sa77 1000110xxx 64/32 460000h?46ffffh 230000h?237fffh sa118 1101111xxx 64/32 6f0000h?6fffffh 378000h?37ffffh sa78 1000111xxx 64/32 470000h?47ffffh 238000h?23ffffh sa119 1110000xxx 64/32 700000h?70ffffh 380000h?387fffh sa79 1001000xxx 64/32 480000h?48ffffh 240000h?247fffh sa120 1110001xxx 64/32 710000h?71ffffh 388000h?38ffffh sa80 1001001xxx 64/32 490000h?49ffffh 248000h?24ffffh sa121 1110010xxx 64/32 720000h?72ffffh 390000h?397fffh sa81 1001010xxx 64/32 4a0000h?4affffh 250000h?257fffh sa122 1110011xxx 64/32 730000h?73ffffh 398000h?39ffffh sa82 1001011xxx 64/32 4b0000h?4bffffh 258000h?25ffffh sa123 1110100xxx 64/32 740000h?74ffffh 3a0000h?3a7fffh sa83 1001100xxx 64/32 4c0000h?4cffffh 260000h?267fffh sa124 1110101xxx 64/32 750000h?75ffffh 3a8000h?3affffh sa84 1001101xxx 64/32 4d0000h?4dffffh 268000h?26ffffh sa125 1110110xxx 64/32 760000h?76ffffh 3b0000h?3b7fffh sa85 1001110xxx 64/32 4e0000h?4effffh 270000h?277fffh sa126 1110111xxx 64/32 770000h?77ffffh 3b8000h?3bffffh sa86 1001111xxx 64/32 4f0000h?4fffffh 278000h?27ffffh sa127 1111000xxx 64/32 780000h?78ffffh 3c0000h?3c7fffh sa87 1010000xxx 64/32 500000h?50ffffh 280000h?28ffffh sa128 1111001xxx 64/32 790000h?79ffffh 3c8000h?3cffffh sa88 1010001xxx 64/32 510000h?51ffffh 288000h?28ffffh sa129 1111010xxx 64/32 7a0000h?7affffh 3d0000h?3d7fffh sa89 1010010xxx 64/32 520000h?52ffffh 290000h?297fffh sa130 1111011xxx 64/32 7b0000h?7bffffh 3d8000h?3dffffh sa90 1010011xxx 64/32 530000h?53ffffh 298000h?29ffffh sa131 1111100xxx 64/32 7c0000h?7cffffh 3e0000h?3e7fffh sa91 1010100xxx 64/32 540000h?54ffffh 2a0000h?2a7fffh sa132 1111101xxx 64/32 7d0000h?7dffffh 3e8000h?3effffh sa92 1010101xxx 64/32 550000h?55ffffh 2a8000h?2affffh sa133 1111110xxx 64/32 7e0000h?7effffh 3f0000h?3f7fffh sa93 1010110xxx 64/32 560000h?56ffffh 2b0000h?2b7fffh sa134 1111111000 64/32 7f0000h?7fffffh 3f8000h?3fffffh sa94 1010111xxx 64/32 570000h?57ffffh 2b8000h?2bffffh table 12. s29gl064a (model r4, w4) b ottom boot sector addresses (sheet 2 of 2) sector a21?a12 sector size (kb/ kwords) 8-bit address range 16-bit address range sector a21?a12 sector size (kb/ kwords) 8-bit address range 16-bit address range
34 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary table 13. s29gl064a (model r5) sector addresses (sheet 1 of 2) sector a21?a15 16-bit address range sector a21?a15 16-bit address range sa0 0000000 000000?007fff sa21 0010101 0a8000?0affff sa1 0000001 008000?00ffff sa22 0010110 0b0000?0b7fff sa2 0000010 010000?017fff sa23 0010111 0b8000?0bffff sa3 0000011 018000?01ffff sa24 0011000 0c0000?0c7fff sa4 0000100 020000?027fff sa25 0011001 0c8000?0cffff sa5 0000101 028000?02ffff sa26 0011010 0d0000?0d7fff sa6 0000110 030000?037fff sa27 0011011 0d8000?0dffff sa7 0000111 038000?03ffff sa28 0011100 0e0000?0e7fff sa8 0001000 040000?047fff sa29 0011101 0e8000?0effff sa9 0001001 048000?04ffff sa30 0011110 0f0000?0f7fff sa10 0001010 050000?057fff sa31 0011111 0f8000?0fffff sa11 0001011 058000?05ffff sa32 0100000 200000?207fff sa12 0001100 060000?067fff sa33 0100001 208000?20ffff sa13 0001101 068000?06ffff sa34 0100010 210000?217fff sa14 0001110 070000?077fff sa35 0100011 218000?21ffff sa15 0001111 078000?07ffff sa36 0100100 220000?227fff sa16 0010000 080000?087fff sa37 0100101 228000?22ffff sa17 0010001 088000?08ffff sa38 0100110 230000?237fff sa18 0010010 090000?097fff sa39 0100111 238000?23ffff sa19 0010011 098000?09ffff sa40 0101000 240000?247fff sa20 0010100 0a0000?0a7fff sa41 0101001 248000?24ffff sa42 0101010 250000?257fff sa85 1010101 1a8000?1affff sa43 0101011 258000?25ffff sa86 1010110 1b0000?1b7fff sa44 0101100 260000?267fff sa87 1010111 1b8000?1bffff sa45 0101101 268000?26ffff sa88 1011000 1c0000?1c7fff sa46 0101110 270000?277fff sa89 1011001 1c8000?1cffff sa47 0101111 278000?27ffff sa90 1011010 1d0000?1d7fff sa48 0110000 280000?287fff sa91 1011011 1d8000?1dffff sa49 0110001 288000?28ffff sa92 1011100 1e0000?1e7fff sa50 0110010 290000?297fff sa93 1011101 1e8000?1effff sa51 0110011 298000?29ffff sa94 1011110 1f0000?1f7fff sa52 0110100 2a0000?2a7fff sa95 1011111 1f8000?1fffff sa53 0110101 2a8000?2affff sa96 1100000 300000?307fff sa54 0110110 2b0000?2b7fff sa97 1100001 308000?30ffff sa55 0110111 2b8000?2bffff sa98 1100010 310000?317fff sa56 0111000 2c0000?2c7fff sa99 1100011 318000?31ffff sa57 0111001 2c8000?2cffff sa100 1100100 320000?327fff sa58 0111010 2d0000?2d7fff sa101 1100101 328000?32ffff sa59 0111011 2d8000?2dffff sa102 1100110 330000?337fff sa60 0111100 2e0000?2e7fff sa103 1100111 338000?33ffff sa61 0111101 2e8000?2effff sa104 1101000 340000?347fff sa62 0111110 2f0000?2f7fff sa105 1101001 348000?34ffff sa63 0111111 2f8000?2fffff sa106 1101010 350000?357fff sa64 1000000 100000?107fff sa107 1101011 358000?35ffff sa65 1000001 108000?10ffff sa108 1101100 360000?367fff sa66 1000010 110000?117fff sa109 1101101 368000?36ffff
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 35 preliminary sa67 1000011 118000?11ffff sa110 1101110 370000?377fff sa68 1000100 120000?127fff sa111 1101111 378000?37ffff sa69 1000101 128000?12ffff sa112 1110000 380000?387fff sa70 1000110 130000?137fff sa113 1110001 388000?38ffff sa71 1000111 138000?13ffff sa114 1110010 390000?397fff sa72 1001000 140000?147fff sa115 1110011 398000?39ffff sa73 1001001 148000?14ffff sa116 1110100 3a0000?3a7fff sa74 1001010 150000?157fff sa117 1110101 3a8000?3affff sa75 1001011 158000?15ffff sa118 1110110 3b0000?3b7fff sa76 1001100 160000?167fff sa119 1110111 3b8000?3bffff sa77 1001101 168000?16ffff sa120 1111000 3c0000?3c7fff sa78 1001110 170000?177fff sa121 1111001 3c8000?3cffff sa79 1001111 178000?17ffff sa122 1111010 3d0000?3d7fff sa80 1010000 180000?187fff sa123 1111011 3d8000?3dffff sa81 1010001 188000?18ffff sa124 1111100 3e0000?3e7fff sa82 1010010 190000?197fff sa125 1111101 3e8000?3effff sa83 1010011 198000?19ffff sa126 1111110 3f0000?3f7fff sa84 1010100 1a0000?1a7fff sa127 1111111 3f8000?3fffff table 13. s29gl064a (model r5) sector addresses (sheet 2 of 2) sector a21?a15 16-bit address range sector a21?a15 16-bit address range
36 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary table 14. s29gl064a (models r6, r7) sector addresses (sheet 1 of 2) sector a21?a15 16-bit address range sector a21?a15 16-bit address range sa0 0000000 000000?007fff sa21 0010101 0a8000?0affff sa1 0000001 008000?00ffff sa22 0010110 0b0000?0b7fff sa2 0000010 010000?017fff sa23 0010111 0b8000?0bffff sa3 0000011 018000?01ffff sa24 0011000 0c0000?0c7fff sa4 0000100 020000?027fff sa25 0011001 0c8000?0cffff sa5 0000101 028000?02ffff sa26 0011010 0d0000?0d7fff sa6 0000110 030000?037fff sa27 0011011 0d8000?0dffff sa7 0000111 038000?03ffff sa28 0011100 0e0000?0e7fff sa8 0001000 040000?047fff sa29 0011101 0e8000?0effff sa9 0001001 048000?04ffff sa30 0011110 0f0000?0f7fff sa10 0001010 050000?057fff sa31 0011111 0f8000?0fffff sa11 0001011 058000?05ffff sa32 0100000 200000?207fff sa12 0001100 060000?067fff sa33 0100001 208000?20ffff sa13 0001101 068000?06ffff sa34 0100010 210000?217fff sa14 0001110 070000?077fff sa35 0100011 218000?21ffff sa15 0001111 078000?07ffff sa36 0100100 220000?227fff sa16 0010000 080000?087fff sa37 0100101 228000?22ffff sa17 0010001 088000?08ffff sa38 0100110 230000?237fff sa18 0010010 090000?097fff sa39 0100111 238000?23ffff sa19 0010011 098000?09ffff sa40 0101000 240000?247fff sa20 0010100 0a0000?0a7fff sa41 0101001 248000?24ffff sa42 0101010 250000?257fff sa85 1010101 1a8000?1affff sa43 0101011 258000?25ffff sa86 1010110 1b0000?1b7fff sa44 0101100 260000?267fff sa87 1010111 1b8000?1bffff sa45 0101101 268000?26ffff sa88 1011000 1c0000?1c7fff sa46 0101110 270000?277fff sa89 1011001 1c8000?1cffff sa47 0101111 278000?27ffff sa90 1011010 1d0000?1d7fff sa48 0110000 280000?287fff sa91 1011011 1d8000?1dffff sa49 0110001 288000?28ffff sa92 1011100 1e0000?1e7fff sa50 0110010 290000?297fff sa93 1011101 1e8000?1effff sa51 0110011 298000?29ffff sa94 1011110 1f0000?1f7fff sa52 0110100 2a0000?2a7fff sa95 1011111 1f8000?1fffff sa53 0110101 2a8000?2affff sa96 1100000 300000?307fff sa54 0110110 2b0000?2b7fff sa97 1100001 308000?30ffff sa55 0110111 2b8000?2bffff sa98 1100010 310000?317fff sa56 0111000 2c0000?2c7fff sa99 1100011 318000?31ffff sa57 0111001 2c8000?2cffff sa100 1100100 320000?327fff sa58 0111010 2d0000?2d7fff sa101 1100101 328000?32ffff sa59 0111011 2d8000?2dffff sa102 1100110 330000?337fff sa60 0111100 2e0000?2e7fff sa103 1100111 338000?33ffff sa61 0111101 2e8000?2effff sa104 1101000 340000?347fff sa62 0111110 2f0000?2f7fff sa105 1101001 348000?34ffff sa63 0111111 2f8000?2fffff sa106 1101010 350000?357fff sa64 1000000 100000?107fff sa107 1101011 358000?35ffff sa65 1000001 108000?10ffff sa108 1101100 360000?367fff
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 37 preliminary autoselect mode the autoselect mode provides manufacturer and device identification, and sector group protection verification, through iden tifier codes output on dq7?dq0. this mode is primarily intended for progra mming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the com - mand register. when using programming equipment, the autoselect mode requires v id on ad - dress pin a9. address pins a6, a3, a2, a1, and a0 must be as shown in ta b l e 15 on page 38 . in addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see ta b l e 7 - ta b l e 25 ). ta b l e 15 on page 38 shows the remaining address bits that are don?t care. when all necessary bits are set as required, the programming equipment may then read the corresponding identifier code on dq7?dq0. to access the autoselect codes in-system, the host system can issue the autose - lect command via the command register, as shown in ta b l e 30 on page 61 and ta b l e 31 on page 62 . this method does not require v id . refer to the autoselect command sequence section for more information. sa66 1000010 110000?117fff sa109 1101101 368000?36ffff sa67 1000011 118000?11ffff sa110 1101110 370000?377fff sa68 1000100 120000?127fff sa111 1101111 378000?37ffff sa69 1000101 128000?12ffff sa112 1110000 380000?387fff sa70 1000110 130000?137fff sa113 1110001 388000?38ffff sa71 1000111 138000?13ffff sa114 1110010 390000?397fff sa72 1001000 140000?147fff sa115 1110011 398000?39ffff sa73 1001001 148000?14ffff sa116 1110100 3a0000?3a7fff sa74 1001010 150000?157fff sa117 1110101 3a8000?3affff sa75 1001011 158000?15ffff sa118 1110110 3b0000?3b7fff sa76 1001100 160000?167fff sa119 1110111 3b8000?3bffff sa77 1001101 168000?16ffff sa120 1111000 3c0000?3c7fff sa78 1001110 170000?177fff sa121 1111001 3c8000?3cffff sa79 1001111 178000?17ffff sa122 1111010 3d0000?3d7fff sa80 1010000 180000?187fff sa123 1111011 3d8000?3dffff sa81 1010001 188000?18ffff sa124 1111100 3e0000?3e7fff sa82 1010010 190000?197fff sa125 1111101 3e8000?3effff sa83 1010011 198000?19ffff sa126 1111110 3f0000?3f7fff sa84 1010100 1a0000?1a7fff sa127 1111111 3f8000?3fffff table 14. s29gl064a (models r6, r7) sector addresses (sheet 2 of 2) sector a21?a15 16-bit address range sector a21?a15 16-bit address range
38 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary ta b l e 1 5 . autoselect codes, (high voltage method) legend: l = logic low = v il , h = logic high = v ih , sa = sector address, x = don?t care. sector group protection and unprotection the hardware sector group protection feature disables both program and erase operations in any sector group (see ta b l e s 14 ? 25 ). the hardware sector group unprotection feature re-enables both prog ram and erase operations in previously protected sector groups. sector group protection/unprotection can be imple - mented via two methods. sector protection/unprotection requires v id on the reset# pin only, and can be implemented either in-system or via programming equipment. figure 2, on page 44 shows the algorithms and figure 24, on page 86 shows the timing diagram. this method uses standard microprocessor bus cycle timing. for sector group unprotect, all unprotected sector groups must first be protected prior to the first sector group unprotect write cycle. the device is shipped with all sector groups unprotected. spansion offers the op - tion of programming and protecting sector groups at its factory prior to shipping the device through spansion programmin g service. contact a spansion repre - sentative for details. it is possible to determine whether a sector group is protected or unprotected. see autoselect mode on page 37 for details. description ce# oe# we# a22 to a15 a14 to a10 a9 a8 to a7 a6 a5 to a4 a3 to a2 a1 a0 dq8 to dq15 dq7 to dq0 model number byte# = v ih byte# = v il r1, r2, w1, w2, r8, r9 r3, r4, w3, w4 r5, r6, r7 manufacturer id : spansion products l l h x x v id x l x l l l 00 x 01h 01h 01h s29gl064a cycle 1 l l h x x v id x l x l l h 22 x 7eh 7eh 7eh cycle 2 h h l 22 x 0ch 10h 13h cycle 3 h h h 22 x 01h 00h (-r4, bottom boot) 01h (-r3, top boot) 01h s29gl032a cycle 1 l l h x x v id x l x l l h 22 x 7eh 7eh cycle 2 h h l 22 x 1dh 1ah cycle 3 h h h 22 x 00h 00h (-r4, bottom boot) 01h (-r3, top boot) s29gl016a cycle 1 l l h x x v id x x x x l h 22 x 49h (-r2, -02, -w2, bottom boot) c4h (-r1, -01, -w1, top boot) sector group protection verification l l h sa x v id x l x l h l x x 01h (protected), 00h (unprotected) secured silicon sector indicator bit (dq7), wp# protects highest address sector l l h x x v id x l x l h h x x for s29gl064a and s29gl032a: 99h (factory locked), 19h (not factory locked) for s29gl016a: 94h (factory locked), 14h (not factory locked) secured silicon sector indicator bit (dq7), wp# protects lowest address sector l l h x x v id x l x l h h x x for s29gl064a and s29gl032a: 89h (factory locked), 09h (not factory locked) for s29gl016a: 84h (factory locked), 04h (not factory locked)
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 39 preliminary table 16. s29gl016a (model r1, 01, w1) sector group protection/unprotection addresses sector a19?a12 sector/sector block size (kbytes) sector a19?a12 sector/sector block size (kbytes) sa0-sa3 000xxxxxh 256 (4x64) sa31 11111000h 8 sa4-sa7 001xxxxxh 256 (4x64) sa32 11111001h 8 sa8-sa11 010xxxxxh 256 (4x64) sa33 11111010h 8 sa12-sa15 011xxxxxh 256 (4x64) sa34 11111011h 8 sa16-sa19 100xxxxxh 256 (4x64) sa35 11111100h 8 sa20-sa23 101xxxxxh 256 (4x64) sa36 11111101h 8 sa24-sa27 110xxxxxh 256 (4x64) sa37 11111110h 8 sa28-sa30 11100xxxh 192 (3x64) sa38 11111111h 8 11101xxxh 11110xxxh ta b l e 1 7 . s29gl016a (model r2, 02, w2) sector gr oup protection/unprotection addresses sector a19?a12 sector/sector block size (kbytes) sector a19?a12 sector/sector block size (kbytes) sa0 00000000h 8 sa8?sa10 00001xxxh 192 (3x64) sa1 00000001h 8 00010xxxh sa2 00000010h 8 00011xxxh sa3 00000011h 8 sa11?sa14 001xxxxxh 256 (4x64) sa4 00000100h 8 sa15?sa18 010xxxxxh 256 (4x64) sa5 00000101h 8 sa19?sa22 011xxxxxh 256 (4x64) sa6 00000110h 8 sa23?sa26 100xxxxxh 256 (4x64) sa7 00000111h 8 sa27-sa30 101xxxxxh 256 (4x64) sa31-sa34 110xxxxxh 256 (4x64) sa35-sa38 111xxxxxh 256 (4x64) ta b l e 1 8 . s29gl032a (models r1, r2, w1, w2) sector group protection/unprotection addresses sector a20?a15 sector /sector block size (kbytes) sector a20?a15 sector /sector block size (kbytes) sector a20?a15 sector /sector block size (kbytes) sector a20?a15 sector /sector block size (kbytes) sa0 000000 64 sa12?sa15 0011xx 256 (4x64) sa36?sa39 1001xx 256 (4x64) sa56?sa59 1110xx 256 (4x64) sa1 000001 64 sa16?sa19 0100xx 256 (4x64) sa40?sa43 1010xx 256 (4x64) sa60 111100 64 sa2 000010 64 sa20?sa23 0101xx 256 (4x64) sa44?sa47 1011xx 256 (4x64) sa61 111101 64 sa3 000011 64 sa24?sa27 0110xx 256 (4x64) sa48?sa51 1100xx 256 (4x64) sa62 111110 64 sa4?sa7 0001xx 256 (4x64) sa28?sa31 0111xx 256 (4x64) sa52?sa55 1101xx 256 (4x64) sa63 111111 64 sa8?sa11 0010xx 256 (4x64) sa32?sa35 1000xx 256 (4x64)
40 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary ta b l e 1 9 . s29gl032a (model r3, w3) sector group protection/unprotection address table sector a20?a12 sector/sector block size (kbytes) sector a20?a12 sector/sector block size (kbytes) sector a20?a12 sector/sector block size (kbytes) sa0-sa3 0000xxxxxh 256 (4x64) sa36?sa39 1001xxxxxh 256 (4x64) sa63 111111000h 8 sa4-sa7 0001xxxxxh 256 (4x64) sa40?sa43 1010xxxxxh 256 (4x64) sa64 111111001h 8 sa8-sa11 0010xxxxxh 256 (4x64) sa44?sa47 1011xxxxxh 256 (4x64) sa65 111111010h 8 sa12-sa15 0011xxxxxh 256 (4x64) sa48?sa51 1100xxxxxh 256 (4x64) sa66 111111011h 8 sa16-sa19 0100xxxxxh 256 (4x64) sa52-sa55 1101xxxxxh 256 (4x64) sa67 111111100h 8 sa20-sa23 0101xxxxxh 256 (4x64) sa56-sa59 1110xxxxxh 256 (4x64) sa68 111111101h 8 sa24-sa27 0110xxxxxh 256 (4x64) sa60-sa62 111100xxxh 192 (3x64) sa69 111111110h 8 sa28-sa31 0111xxxxxh 256 (4x64) 111101xxxh sa70 111111111h 8 sa32?sa35 1000xxxxxh 256 (4x64) 111110xxxh table 20. s29gl032a (model r4, w4) sector group protection/unprotection address table sector a20?a12 sector/sector block size (kbytes) sector a20?a12 sector/sector block size (kbytes) sector a20?a12 sector/sector block size (kbytes) sa0 000000000h 8 sa8?sa10 000001xxxh 192 (3x64) sa35-sa38 0111xxxxxh 256 (4x64) sa1 000000001h 8 000010xxxh sa39-sa42 1000xxxxxh 256 (4x64) sa2 000000010h 8 000011xxxh sa43-sa46 1001xxxxxh 256 (4x64) sa3 000000011h 8 sa11?sa14 0001xxxxxh 256 (4x64) sa47-sa50 1010xxxxxh 256 (4x64) sa4 000000100h 8 sa15?sa18 0010xxxxxh 256 (4x64) sa51-sa54 1011xxxxxh 256 (4x64) sa5 000000101h 8 sa19?sa22 0011xxxxxh 256 (4x64) sa55?sa58 1100xxxxxh 256 (4x64) sa6 000000110h 8 sa23?sa26 0100xxxxxh 256 (4x64) sa59?sa62 1101xxxxxh 256 (4x64) sa7 000000111h 8 sa27-sa30 0101xxxxxh 256 (4x64) sa63?sa66 1110xxxxxh 256 (4x64) sa31-sa34 0110xxxxxh 256 (4x64) sa67?sa70 1111xxxxxh 256 (4x64) ta b l e 2 1 . s29gl064a (models r1, r2, r8, r9, w1, w2) sect or group protection/unprotection addresses sector a21?a15 sector/ sector block size (kbytes) sector a21?a15 sector/ sector block size (kbytes) sector a21?a15 sector/ sector block size (kbytes) sector a21?a15 sector/ sector block size (kbytes) sa0 0000000 64 sa28?sa31 00111xx 256 (4x64) sa68?sa71 10001xx 256 (4x64) sa108?sa111 11011xx 256 (4x64) sa1 0000001 64 sa32?sa35 01000xx 256 (4x64) sa72?sa75 10010xx 256 (4x64) sa112?sa115 11100xx 256 (4x64) sa2 0000010 64 sa36?sa39 01001xx 256 (4x64) sa76?sa79 10011xx 256 (4x64) sa116?sa119 11101xx 256 (4x64) sa3 0000011 64 sa40?sa43 01010xx 256 (4x64) sa80?sa83 10100xx 256 (4x64) sa120?sa123 11110xx 256 (4x64) sa4?sa7 00001xx 256 (4x64) sa44?sa47 01011xx 256 (4x64) sa84?sa87 10101xx 256 (4x64) sa124 1111100 64 sa8?sa11 00010xx 256 (4x64) sa48?sa51 01100xx 256 (4x64) sa88?sa91 10110xx 256 (4x64) sa125 1111101 64 sa12?sa15 00011xx 256 (4x64) sa52?sa55 01101xx 256 (4x64) sa92?sa95 10111xx 256 (4x64) sa126 1111110 64 sa16?sa19 00100xx 256 (4x64) sa56?sa59 01110xx 256 (4x64) sa96?sa99 11000xx 256 (4x64) sa127 1111111 64 sa20?sa23 00101xx 256 (4x64) sa60?sa63 01111xx 256 (4x64) sa100?sa103 11001xx 256 (4x64) sa24?sa27 00110xx 256 (4x64) sa64?sa67 10000xx 256 (4x64) sa104?sa107 11010xx 256 (4x64)
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 41 preliminary table 22. s29gl064a (model r3, w3) top boot sect or protection/unprotection addresses sector a21?a12 sector/sector block size (kbytes) sector a20?a12 sector/sector block size (kbytes) sector a20?a12 sector/sector block size (kbytes) sa0-sa3 00000xxxxx 256 (4x64) sa56-sa59 01110xxxxx 256 (4x64) sa112-sa115 11100xxxxx 256 (4x64) sa4-sa7 00001xxxxx 256 (4x64) sa60-sa63 01111xxxxx 256 (4x64) sa116-sa119 11101xxxxx 256 (4x64) sa8-sa11 00010xxxxx 256 (4x64) sa64-sa67 10000xxxxx 256 (4x64) sa120-sa123 11110xxxxx 256 (4x64) sa12-sa15 00011xxxxx 256 (4x64) sa68-sa71 10001xxxxx 256 (4x64) sa124-sa126 1111100xxx 1111101xxx 1111110xxx 192 (3x64) sa16-sa19 00100xxxxx 256 (4x64) sa72-sa75 10010xxxxx 256 (4x64) sa127 1111111000 8 sa20-sa23 00101xxxxx 256 (4x64) sa76-sa79 10011xxxxx 256 (4x64) sa128 1111111001 8 sa24-sa27 00110xxxxx 256 (4x64) sa80-sa83 10100xxxxx 256 (4x64) sa129 1111111010 8 sa28-sa31 00111xxxxx 256 (4x64) sa84-sa87 10101xxxxx 256 (4x64) sa130 1111111011 8 sa32-sa35 01000xxxxx 256 (4x64) sa88-sa91 10110xxxxx 256 (4x64) sa131 1111111100 8 sa36-sa39 01001xxxxx 256 (4x64) sa92-sa95 10111xxxxx 256 (4x64) sa132 1111111101 8 sa40-sa43 01010xxxxx 256 (4x64) sa96-sa99 11000xxxxx 256 (4x64) sa133 1111111110 8 sa44-sa47 01011xxxxx 256 (4x64) sa100-sa103 11001xxxxx 256 (4x64) sa134 1111111111 8 sa48-sa51 01100xxxxx 256 (4x64) sa104-sa107 11010xxxxx 256 (4x64) sa52-sa55 01101xxxxx 256 (4x64) sa108-sa111 11011xxxxx 256 (4x64) table 23. s29gl064a (model r4, w4) bottom boot sector protection/unprotection addresses sector a21?a12 sector/sector block size (kbytes) sector a20?a12 sector/sector block size (kbytes) sector a20?a12 sector/sector block size (kbytes) sa0 0000000000 8 sa31-sa34 00110xxxxx 256 (4x64) sa87?sa90 10100xxxxx 256 (4x64) sa1 0000000001 8 sa35-sa38 00111xxxxx 256 (4x64) sa91?sa94 10101xxxxx 256 (4x64) sa2 0000000010 8 sa39-sa42 01000xxxxx 256 (4x64) sa95?sa98 10110xxxxx 256 (4x64) sa3 0000000011 8 sa43-sa46 01001xxxxx 256 (4x64) sa99?sa102 10111xxxxx 256 (4x64) sa4 0000000100 8 sa47-sa50 01010xxxxx 256 (4x64) sa103?sa106 11000xxxxx 256 (4x64) sa5 0000000101 8 sa51-sa54 01011xxxxx 256 (4x64) sa107?sa110 11001xxxxx 256 (4x64) sa6 0000000110 8 sa55?sa58 01100xxxxx 256 (4x64) sa111?sa114 11010xxxxx 256 (4x64) sa7 0000000111 8 sa59?sa62 01101xxxxx 256 (4x64) sa115?sa118 11011xxxxx 256 (4x64) sa8?sa10 0000001xxx, 0000010xxx, 0000011xxx, 192 (3x64) sa63?sa66 01110xxxxx 256 (4x64) sa119?sa122 11100xxxxx 256 (4x64) sa11?sa14 00001xxxxx 256 (4x64) sa67?sa70 01111xxxxx 256 (4x64) sa123?sa126 11101xxxxx 256 (4x64) sa15?sa18 00010xxxxx 256 (4x64) sa71?sa74 10000xxxxx 256 (4x64) sa127?sa130 11110xxxxx 256 (4x64) sa19?sa22 00011xxxxx 256 (4x64) sa75?sa78 10001xxxxx 256 (4x64) sa131?sa134 11111xxxxx 256 (4x64) sa23?sa26 00100xxxxx 256 (4x64) sa79?sa82 10010xxxxx 256 (4x64) sa27-sa30 00101xxxxx 256 (4x64) sa83?sa86 10011xxxxx 256 (4x64)
42 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary ta b l e 2 4 . s29gl064a (model r5) sector group protection/unprotection addresses sector a21?a15 sector/ sector block size (kbytes) sector a21?a15 sector/ sector block size (kbytes) sector a21?a15 sector/ sector block size (kbytes) sector a21?a15 sector/ sector block size (kbytes) sa0?sa3 00000 256 (4x64) sa32?sa35 01000 256 (4x64) sa64?sa67 10000 256 (4x64) sa96?sa99 11000 256 (4x64) sa4?sa7 00001 256 (4x64) sa36?sa39 01001 256 (4x64) sa68?sa71 10001 256 (4x64) sa100?sa103 11001 256 (4x64) sa8?sa11 00010 256 (4x64) sa40?sa43 01010 256 (4x64) sa72?sa75 10010 256 (4x64) sa104?sa107 11010 256 (4x64) sa12?sa15 00011 256 (4x64) sa44?sa47 01011 256 (4x64) sa76?sa79 10011 256 (4x64) sa108?sa111 11011 256 (4x64) sa16?sa19 00100 256 (4x64) sa48?sa51 01100 256 (4x64) sa80?sa83 10100 256 (4x64) sa112?sa115 11100 256 (4x64) sa20?sa23 00101 256 (4x64) sa52?sa55 01101 256 (4x64) sa84?sa87 10101 256 (4x64) sa116?sa119 11101 256 (4x64) sa24?sa27 00110 256 (4x64) sa56?sa59 01110 256 (4x64) sa88?sa91 10110 256 (4x64) sa120?sa123 11110 256 (4x64) sa28?sa31 00111 256 (4x64) sa60?sa63 01111 256 (4x64) sa92?sa95 10111 256 (4x64) sa124?sa127 11111 256 (4x64) ta b l e 2 5 . s29gl064a (models r6, r7) sector grou p protection/unprotection addresses sector a21?a15 sector/ sector block size (kbytes) sector a21?a15 sector/ sector block size (kbytes) sector a21?a15 sector/ sector block size (kbytes) sector a21?a15 sector/ sector block size (kbytes) sa0?sa3 00000 256 (4x64) sa32?sa35 01000 256 (4x64) sa64?sa67 10000 256 (4x64) sa96?sa99 11000 256 (4x64) sa4?sa7 00001 256 (4x64) sa36?sa39 01001 256 (4x64) sa68?sa71 10001 256 (4x64) sa100?sa103 11001 256 (4x64) sa8?sa11 00010 256 (4x64) sa40?sa43 01010 256 (4x64) sa72?sa75 10010 256 (4x64) sa104?sa107 11010 256 (4x64) sa12?sa15 00011 256 (4x64) sa44?sa47 01011 256 (4x64) sa76?sa79 10011 256 (4x64) sa108?sa111 11011 256 (4x64) sa16?sa19 00100 256 (4x64) sa48?sa51 01100 256 (4x64) sa80?sa83 10100 256 (4x64) sa112?sa115 11100 256 (4x64) sa20?sa23 00101 256 (4x64) sa52?sa55 01101 256 (4x64) sa84?sa87 10101 256 (4x64) sa116?sa119 11101 256 (4x64) sa24?sa27 00110 256 (4x64) sa56?sa59 01110 256 (4x64) sa88?sa91 10110 256 (4x64) sa120?sa123 11110 256 (4x64) sa28?sa31 00111 256 (4x64) sa60?sa63 01111 256 (4x64) sa92?sa95 10111 256 (4x64) sa124?sa127 11111 256 (4x64)
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 43 preliminary temporary sector group unprotect this feature allows temporary unprotection of previously protected sector groups to change data in-system. the sector group unprotect mode is activated by setting the reset# pin to v id . during this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. once v id is removed from the reset# pin, all the previously protected sector groups are protected again. figure 1 shows the algorithm, and figure 22, on page 82 shows the timing diagrams, for this feature. notes: 1. all protected sector groups unprotected (if wp# = v il , the highest or lowest address sector remains protected for uniform sector devices; the top or bottom two address sectors remains protected for boot sector devices). 2. all previously protected sector groups are protected once again. figure 1. temporary sector group unprotect operation start perform erase or program operations reset# = v ih tem p o ra r y s e c t o r group unprotect completed (note 2) reset# = v id (note 1)
44 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary figure 2. in-system sector group protect/unprotect algorithms sector group protect: write 60h to sector group address with a6?a0 = 0xx0010 set up sector group address wait 150 s verify sector group protect: write 40h to sector group address with a6?a0 = 0xx0010 read from sector group address with a6?a0 = 0xx0010 start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector group protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector group unprotect mode no sector group unprotect: write 60h to sector group address with a6?a0 = 1xx0010 set up first sector group address wait 15 ms verify sector group unprotect: write 40h to sector group address with a6?a0 = 1xx0010 read from sector group address with a6?a0 = 1xx0010 start plscnt = 1 reset# = v id wait 1 s data = 00h? last sector group verified? remove v id from reset# write reset command sector group unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary sector group unprotect mode no all sector groups protected? yes protect all sector groups: the indicated portion of the sector group protect algorithm must be performed for all unprotected sector groups prior to issuing the first sector group unprotect address set up next sector group address no yes no yes no no yes no sector group protect algorithm sector group unprotect algorithm first write cycle = 60h? protect another sector group? reset plscnt = 1
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 45 preliminary secured silicon sector flash memory region the secured silicon sector feature provid es a flash memory region that enables permanent part identification through an electronic serial number (esn). the secured silicon sector is 256 bytes in le ngth, and uses a secured silicon sector indicator bit (dq7) to indicate whethe r or not the secured silicon sector is locked when shipped from the factory. th is bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. this en - sures the security of the esn once th e product is shipped to the field. the factory offers the device with the secured silicon sector either customer lockable (standard shipping option) or factory locked (contact a spansion sales representative for ordering information). the customer-lockable version is shipped with the secured silicon sector unprotected, allowing customers to pro - gram the sector after receiving the device. the customer-lockable version also contains the secured silicon sector indicator bit permanently set to a 0 . the fac - tory-locked version is always protected when shipped from the factory, and has the secured silicon sector indicator bit permanently set to a 1 . thus, the se - cured silicon sector indicator bit prevents customer-lockable devices from being used to replace devices that are factory locked. note that the acc function and unlock bypass modes are not available when the secured silicon sector is enabled. the secured silicon sector address space in this device is allocated as follows: the system accesses the secured silicon sector through a command sequence (see write protect (wp#) on page 46 ). after the system writes the enter se - cured silicon sector command sequence, it may read the secured silicon sector by using the addresses normally occupied by the first sector (sa0). this mode of operation continues until the system issues the exit secured silicon sector command sequence, or until power is re moved from the device. on power-up, or following a hardware reset, the device reverts to sending commands to sector sa0. customer lockable: secured silic on sector not programmed or protected at the factory unless otherwise specified, the device is shipped such that the customer may program and protect the 256-byte secured silicon sector. the system may program the secured silic on sector using the write-buffer, ac - celerated and/or unlock bypass meth ods, in addition to the standard programming command sequence. see command definitions on page 50 . programming and protecting the secured s ilicon sector must be used with cau - tion since, once protected, there is no procedure available for unprotecting the secured silicon sector area and none of the bits in the secured silicon sector memory space can be modified in any way. the secured silicon sector area can be protected using one of the following procedures: secured silicon sector address range standard factory locked expressflash factory locked customer lockable x16 x8 000000h?000007h 000000h-00000fh esn esn or determined by customer determined by customer 000008h?00007fh 000010h-0000ffh unavailable determined by customer
46 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary ? write the three-cycle enter secured silicon sector region command se- quence, and then follow the in-system sector protect algorithm as shown in figure 2, on page 44 , except that reset# may be at either v ih or v id . this allows in-system protection of the secured silicon sector without raising any device pin to a high voltage. note that this method is only applicable to the secured silicon sector. ? write the three-cycle enter secured silicon sector region command se- quence, and then use the alternate method of sector protection described in the sector group protection and unprotection on page 38 section. once the secured silicon sector is prog rammed, locked and verified, the system must write the exit secured silicon sect or region command sequence to return to reading and writing within the remainder of the array. factory locked: secured silic on sector programmed and protected at the factory in devices with an esn, the secured silicon sector is protected when the device is shipped from the factory. the secured silicon sector cannot be modified in any way. an esn factory locked device has an 16-byte random esn at addresses 000000h?000007h. please contact your sales representative for details on or - dering esn factory locked devices. customers may opt to have their code programmed by the factory through the spansion programming service (customer factory locked). the devices are then shipped from the factory with the secu red silicon sector permanently locked. contact your sales representative for details on using th e spansion program - ming service. write protect (wp#) the write protect function provides a hard ware method of protecting the first or last sector group without using v id . write protect is one of two functions pro - vided by the wp#/acc input. if the system asserts v il on the wp#/acc pin, the device disables program and erase functions in the first or last sector group independently of whether those sector groups were protected or unprotected. note that if wp#/acc is at v il when the device is in the standby mode, the maximum input load current is in - creased. see the table in dc characteristics on page 71 . if the system asserts v ih on the wp#/acc pin, the device reverts to whether the first or last sector was previously set to be protected or un - protected using the method described in sector group protection and unprotection on page 38 . note that wp# contains an internal pullup; when unconnected, wp# is at v ih . hardware data protection the command sequence requirement of unlock cycles for programming or eras - ing provides data protection agai nst inadvertent writes (refer to ta b l e 30 on page 61 and ta b l e 31 on page 62 for command definitions). in addition, the fol - lowing hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise.
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 47 preliminary low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to the read mode. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . write pulse glitch protection noise pulses of less than 3 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automati - cally reset to the read mode on power-up. common flash memory interface (cfi) the common flash interface (cfi) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified soft - ware algorithms to be used for entire families of devices. software support can then be device-independent, jedec id-independent, and forward- and back - ward-compatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h, any time th e device is ready to read array data. the system can read cfi information at the addresses given in ta b l e s 26 ? 29 . to terminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the au - toselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in ta b l e s 26 ? 29 . the system must write the reset command to return the device to reading array data. for further information, please refer to the cfi specification and cfi publication 100. alternatively, contact your sales representative for copies of these documents.
48 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary note: cfi data related to v cc and time-outs may differ from actual v cc and time-outs of the product. please consult the ordering information tables to obtain the v cc range for particular part numbers. please co nsult the erase and progra mming performance table for typical timeou t specifications. table 26. cfi query identification string addresses (x16) addresses (x8) data description 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 26h 28h 0002h 0000h primary oem command set 15h 16h 2ah 2ch 0040h 0000h address for primary extended table 17h 18h 2eh 30h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 32h 34h 0000h 0000h address for alternate oem extended table (00h = none exists) table 27. system interface string addresses (x16) addresses (x8) data description 1bh 36h 0027h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 38h 0036h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 3ah 0000h v pp min. voltage (00h = no v pp pin present) 1eh 3ch 0000h v pp max. voltage (00h = no v pp pin present) 1fh 3eh 0007h reserved for future use 20h 40h 0007h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 42h 000ah typical timeout per individual block erase 2 n ms 22h 44h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 46h 0001h reserved for future use 24h 48h 0005h max. timeout for buffer write 2 n times typical 25h 4ah 0004h max. timeout per individual block erase 2 n times typical 26h 4ch 0000h max. timeout for full chip erase 2 n times typical (00h = not supported) ta b l e 2 8 . device geometry definition (sheet 1 of 2) addresses (x16) addresses (x8) data description 27h 4eh 00xxh device size = 2 n byte 0017h = 64 mb, 0016h = 32mb, 0015h = 16mb 28h 29h 50h 52h 000xh 0000h flash device interface description (refer to cfi publication 100) 0000h = x8-only bus devices 0001h = x16-only bus devices 0002h = x8/x16 bus devices 2ah 2bh 54h 56h 0005h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 58h 00xxh number of erase block regions within device (01h = uniform device, 02h = boot device) 2dh 2eh 2fh 30h 5ah 5ch 5eh 60h 00xxh 000xh 00x0h 000xh erase block region 1 information (refer to the cfi specification or cfi publication 100) 0000h, 0020h, 0000h, 0007h = 16 mb (-r1, -r2) 007fh, 0000h, 0020h, 0000h = 32 mb (-r1, -r2) 003fh, 0000h, 0001h = 32 mb (-r3, r4) 007fh, 0000h, 0020h, 0000h = 64 mb (-r1, -r2, -r8, -r9) 007fh, 0000h, 0000h, 0001h = 64 mb (-r3, -r4, -r5, -r6, -r7)
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 49 preliminary 31h 32h 33h 34h 60h 64h 66h 68h 00xxh 0000h 0000h 000xh erase block region 2 information (refer to cfi publication 100) 0001h, 0000h, 0000h, 001eh = 16 mb (-r1, -r2) 003eh, 0000h, 0000h, 0001h = 32 mb (-r1, -r2) 007eh, 0000h, 0000h, 0001h = 64 mb (-r1, -r2, -r8, -r9) 0000h, 0000h, 0000h, 0000h = all others 35h 36h 37h 38h 6ah 6ch 6eh 70h 0000h 0000h 0000h 0000h erase block region 3 information (refer to cfi publication 100) 39h 3ah 3bh 3ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h erase block region 4 information (refer to cfi publication 100) table 29. primary vendor-specific extended query addresses (x16) addresses (x8) data description 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 86h 0031h major version number, ascii 44h 88h 0033h minor version number, ascii 45h 8ah 000xh address sensitive unlock (bits 1-0) 0 = required, 1 = not required process technology (bits 7-2) 0010b = 200 nm mirrorbit 0009h = x8-only bus devices 0008h = all other devices 46h 8ch 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 8eh 0001h sector protect 0 = not supported, x = number of sectors in smallest sector group 48h 90h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 92h 0004h sector protect/un protect scheme 0004h = standard mode (refer to text) 4ah 94h 0000h simultaneous operation 00 = not supported, x = number of sectors in bank 4bh 96h 0000h burst mode type 00 = not supported, 01 = supported 4ch 98h 0001h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 9ah 00b5h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 9ch 00c5h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 9eh 00xxh top/bottom boot sector flag 02h = bottom boot device, 03h = top boot device, 04h = uniform sectors bottom wp# protect, 05h = uniform sectors top wp# protect 50h a0h 0001h program suspend 00h = not supported, 01h = supported table 28. device geometry definition (sheet 2 of 2) addresses (x16) addresses (x8) data description
50 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary command definitions writing specific address and data commands or sequences into the command register initiates device operations. ta b l e 30 on page 61 and ta b l e 31 on page 62 define the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. a reset command is then required to return the device to reading array data. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to the ac characteristics section for timing diagrams. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is ready to read array data after completing an embedded prog ram or embedded erase algorithm. after the device accepts an erase su spend command, the device enters the erase-suspend-read mode, after which the system can read data from any non- erase-suspended sector. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same ex - ception. see erase suspend/erase resume commands on page 59 for more information. the system must issue the reset command to return the device to the read (or erase-suspend-read) mode if dq5 goes high during an active program or erase operation, or if the device is in the au toselect mode. see the next section, reset command, for more information. see also requirements for reading array data in the device bus operations sec - tion for more information. the read-only operations? ac characteristics on page 73 provide the read parameters, and figure 13, on page 74 shows the tim - ing diagram. reset command writing the reset command resets the devi ce to the read or erase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the device to the read mode. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the device to the read mode. if the program command sequence is written while the device is in the erase suspend mode, writing the reset command returns the device to the erase-suspend-read mode. once programming begins, however, the device ig - nores reset commands until the operation is complete. the reset command may be written between the sequence cycles in an autose - lect command sequence. once in the autoselect mode, the reset command must be written to return to the read mode. if the device entered the autoselect mode while in the erase suspend mode, writin g the reset command returns the device to the erase-suspend-read mode.
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 51 preliminary if dq5 goes high during a program or erase operation, writing the reset com - mand returns the device to the read mode (or erase-suspend-read mode if the device was in erase suspend). note that if dq1 goes high during a write buffer programming operation, the system must write the write-to-buffer-abort reset command sequence to reset the device for the next operation. autoselect command sequence the autoselect command sequence allows the host system to read several iden - tifier codes at specific addresses: note: the device id is read over three cycles. sa = sector address the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle th at contains the autoselect command. the device then enters the autoselect mode. the system may read at any address any number of times without initiating another autoselect command sequence: the system must write the reset command to return to the read mode (or erase- suspend-read mode if the device was previously in erase suspend). enter/exit secured silicon sector command sequence the secured silicon sector region provides a secured data area containing an 8-word/16-byte random electronic serial number (esn). the system can access the secured silicon sector region by issuing the three-cycle enter secured sili - con sector command sequence. the device continues to access the secured silicon sector region until the system issu es the four-cycle exit secured silicon sector command sequence. the exit secu red silicon sector command sequence returns the device to normal operation. ta b l e 30 on page 61 and ta b l e 31 on page 62 show the address and data requirements for both command sequences. see also secured silicon se ctor flash memory region on page 45 for further in - formation. note that the acc function and unlock bypass modes are not available when the secured silicon sector is enabled. word program co mmand sequence programming is a four-bus-cycle operat ion. the program command sequence is initiated by writing two unlock write cycl es, followed by the program set-up com - mand. the program address and data are wr itten next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timings. the device automatically provides internally generated pro - gram pulses and verifies the programmed cell margin. ta b l e 30 on page 61 and ta b l e 31 on page 62 show the address and data requirements for the word pro - gram command sequence, respectively. identifier code a7:a0 (x16) a6:a-1 (x8) manufacturer id 00h 00h device id, cycle 1 01h 02h device id, cycle 2 0eh 1ch device id, cycle 3 0fh 1eh secured silicon sector factory protect 03h 06h sector protect verify (sa)02h (sa)04h
52 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary when the embedded program algorithm is complete, the device then returns to the read mode and addresses are no long er latched. the system can determine the status of the program operation by using dq7 or dq6. refer to the write op - eration status section for information on these status bits. any commands written to the device during the embe dded program algorithm are ignored. note that the secured silicon sector, autoselect, and cfi functions are unavailable when a program operation is in progress. note that a hardware reset immedi - ately terminates the program operation. the program command sequence should be reinitiated once the device re turns to the read mode, to ensure data integrity. programming is allowed in any sequence of address locations and across sector boundaries. programming to the same wo rd address multiple times without in - tervening erases (incremental bit programming) requires a modified programming method. for such application requirements, please contact your local spansion representative. word pr ogramming is supported for backward compatibility with existing flash driver software and for occasional writing of in - dividual words. use of write buffer programming (see below) is strongly recommended for general programming use when more than a few words are to be programmed. the effective word programming time using write buffer pro - gramming is approximately four times shorter than the single word programming time. any bit in a word cannot be programmed from 0 back to a 1 . attempting to do so may cause the device to set dq5=1, or cause dq7 and dq6 status bits to indicate the operation was successful. however, a succeeding read shows that the data is still 0 . only erase operations can convert a 0 to a 1 . unlock bypass command sequence the unlock bypass feature allows the system to program words to the device faster than using the standard program command sequence. the unlock bypass command sequence is initiated by first wr iting two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. the device then enters the unlock bypass mode. a two-cycle unlock bypass mode command sequence is all that is required to prog ram in this mode. the first cycle in this sequence contains the unlock bypass pr ogram command, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with th e initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. ta b l e 30 on page 61 and ta b l e 31 on page 62 show the requirements for the command sequence. during the unlock bypass mode, only the unlock bypass program and unlock by - pass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. the first cycle must contain the data 90h. the second cycle must contain the data 00h. the de - vice then returns to the read mode. write buffer programming write buffer programming allows the sy stem write to a maximum of 16 words/ 32 bytes in one programming operation. this results in faster effective program - ming time than the standard progra mming algorithms. the write buffer programming command sequence is initiate d by first writing two unlock cycles. this is followed by a third write cycle containing the write buffer load command written at the sector address in whic h programming occurs. the fourth cycle
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 53 preliminary writes the sector address and the number of word locations, minus one, to be programmed. for example, if the system programs six unique address locations, then 05h should be written to the device . this tells the device how many write buffer addresses are loaded with data an d therefore when to expect the program buffer to flash command. the number of locations to program cannot exceed the size of the write buffer or the operation aborts. the fifth cycle writes the first address location and data to be programmed. the write-buffer-page is selected by address bits a max ?a 4 . all subsequent address/ data pairs must fall within the selected-write-buffer-page. the system then writes the remaining address/data pairs into the write buffer. write buffer loca - tions may be loaded in any order. the write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (this me ans write buffer programming cannot be performed across multiple write-buffer page s.) this also means that write buffer programming cannot be performed across multiple sectors. if the system at - tempts to load programming data outside of the selected write-buffer page, the operation aborts. note that if a write buffer address locati on is loaded multiple times, the address/ data pair counter is decremented for ever y data load operation. the host system must therefore account for loading a writ e-buffer location more than once. the counter decrements for each data load operation, not for each unique write- buffer-address location. note also that if an address location is loaded more than once into the buffer, the final data lo aded for that address is programmed. once the specified number of write buffer locations are loaded, the system must then write the program buffer to flash command at the sector address. any other address and data combination abor ts the write buffer programming oper - ation. the device then begins progra mming. data polling should be used while monitoring the last address location lo aded into the write buffer. dq7, dq6, dq5, and dq1 should be monitored to de termine the device status during write buffer programming. the write-buffer programming operation can be suspended using the standard program suspend/resume commands. upon successful completion of the write buffer programming operation, the de vice is ready to execute the next command. the write buffer programming sequence can be aborted in the following ways: ? load a value that is greater than the pa ge buffer size during the number of locations to program step. ? write to an address in a sector differe nt than the one specified during the write-buffer-load command. ? write an address/data pair to a different write-buffer-page than the one se- lected by the starting address during the write buffer data loading stage of the operation. ? write data other than the confirm command after the specified number of data load cycles. the abort condition is indicated by dq1 = 1 , dq7 = data# (for the last address location loaded), dq6 = toggle, and dq5= 0 . a write-to-buffer-abort reset command sequence must be written to re set the device for the next operation. note that the secured silicon sector, au toselect, and cfi functions are unavail - able when a program operation is in progress. this flash device is capable of handling multiple write buffer programmin g operations on the same write buffer address range without intervening erases. for applications requiring incremental
54 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary bit programming, a modified programming method is required; please contact your local spansion representative. any bit in a write buffer address range cannot be programmed from 0 back to a 1 . attempting to do so may cause the device to set dq5=1, of cause the dq7 and dq6 status bits to indicate the operation was successful. however, a succeed ing read shows that the data is still 0 . only erase operations can convert a 0 to a 1 . accelerated program the device offers accelerated program operations through the wp#/acc or acc pin depending on the particular product. when the system asserts v hh on the wp#/acc or acc pin. the device uses the higher voltage on the wp#/acc or acc pin to accelerate the operation. note that the wp#/ acc pin must not be at v hh for operations other than accelerate d programming, or device damage may result. wp# contains an internal pu llup; when unconnected, wp# is at v ih . figure 3, on page 55 illustrates the algorithm for the program operation. refer to the erase and program operations? ac characteristics on page 73 for param - eters, and figure 14, on page 75 for timing diagrams.
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 55 preliminary notes: 1. when sector address is specified, any address in the selected sector is acceptable. however, when loading write-buffer address locations with data, al l addresses must fall within the selected write- buffer page. 2. dq7 may change simultaneously with dq5. therefore, dq7 should be verified. 3. if this flowchart location was reached because dq5= 1 , then the device failed. if this flowchart location was reached because dq1= 1 , then the write to buffer operation was aborted. in either case, the proper reset command must be written before the device can begin another operation. if dq1= 1 , write the write-buffer-programming-abort-reset command. if dq5= 1 , write the reset command. 4. see table 30 on page 61 and table 31 on page 62 for command sequences required for write buffer programming. figure 3. write buffer programming operation write ?write to buffer? command and sector address write number of addresses to program minus 1(wc) and sector address write program buffer to flash sector address write first address/data write to a different sector address fail or abort pass read dq7 - dq0 at last loaded address read dq7 - dq0 with address = last loaded address write next address/data pair wc = wc - 1 wc = 0 ? part of ?write to buffer? command sequence ye s ye s ye s ye s ye s ye s no no no no no no abort write to buffer operation? dq7 = data? dq7 = data? dq5 = 1? dq1 = 1? write to buffer aborted. must write ?write-to-buffer abort reset? command sequence to return to read mode. (note 2) (note 3) (note 1)
56 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary note: see table 30 on page 61 and table 31 on page 62 for program command sequence . figure 4. program operation program suspend/program resume command sequence the program suspend command allows th e system to interrupt a programming operation or a write to buffer programming operation so that data can be read from any non-suspended sector. when the program suspend command is writ - ten during a programming process, the device halts the program operation within 15 s maximum (5 s typical) and updates the status bits. addresses are not required when writing the program suspend command. after the programming operation is suspended, the system can read array data from any non-suspended sector. the pr ogram suspend command may also be issued during a programming operation while an erase is suspended. in this case, data may be read from any addresses not in erase suspend or program suspend. if a read is needed from the secured silicon sector area (one-time program area), then user must use the proper command sequences to enter and exit this region. note that the secured silicon sector, autoselect, and cfi func - tions are unavailable when a program operation is in progress. the system may also write the autoselect command sequence when the device is in the program suspend mode. the system can read as many autoselect codes as required. when the device exits the autoselect mode, the device reverts to the program suspend mode, and is read y for another valid operation. see au - toselect command sequence on page 51 for more information. after the program resume command is written, the device reverts to program - ming. the system can determine the stat us of the program operation using the start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 57 preliminary dq7 or dq6 status bits, just as in the standard program operation. see write operation status on page 63 for more information. the system must write the program resume command (address bits are don?t care) to exit the program suspend mode and continue the programming opera - tion. further writes of the resume command are ignored. another program suspend command can be written after the device resumes programming. figure 5. program suspend/program resume chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is ini - tiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not re - quire the system to preprogram prior to erase. the embedded erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any con - trols or timings during these operations. ta b l e 30 on page 61 and ta b l e 31 on page 62 show the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is co mplete, the device returns to the read mode and addresses are no longer latched. the system can determine the status of the erase operation by using dq7, dq6, or dq2. refer to write operation sta - tus on page 63 for information on these status bits. any commands written during the chip erase operation are ignored. however, note that a hardware reset immediately terminates the erase operation. if this program operation or write-to-buffer sequence in progress write program suspend command sequence command is also valid for erase-suspended-program operations autoselect and secsi sector read operations are also allowed data cannot be read from erase- o r program-suspended sectors write program resume command sequence read data as required done reading? no yes write address/data xxxh/30h device reverts to operation prior to program suspend write address/data xxxh/b0h wait 15 s
58 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary occurs, the chip erase command sequence should be reinitiated once the device returns to reading array data , to ensure data integrity. figure 6, on page 59 illustrates the algorithm for the erase operation. refer to ta b l e 38 on page 76 for parameters, and figure 18, on page 80 for timing diagrams. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycl es, followed by a set-up command. two ad - ditional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. ta b l e 30 on page 61 and ta b l e 31 on page 62 shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram prior to erase. the em - bedded erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of 50 s occurs. during the time-out period, additional sector addresses and sector erase com - mands may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise erasure may begin. any sector erase address and command follow ing the exceeded time-out may or may not be accepted. it is recommended that processor inter - rupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. any command other than sector erase or erase suspend during the time-out period resets the devi ce to the read mode. note that the secured silicon sector, autoselect, and cfi function s are unavailable when an erase op - eration is in progress. the system must rewrite the command sequence and any additional addresses and commands. the system can monitor dq3 to determine if the sector erase timer has timed out (see the section on dq3: sector erase timer.). the time-out begins from the rising edge of the final we# pulse in the command sequence. when the embedded erase algorithm is co mplete, the device returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by reading dq7, dq6, or dq2 in the erasing sector. refer to the write operation status section for information on these status bits. once the sector erase operation begins , only the erase suspend command is valid. all other commands are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once the device returns to reading array data, to ensure data integrity. figure 6, on page 59 illustrates the algorithm for the erase operation. refer to ta b l e 38 on page 76 for parameters, and figure 18, on page 80 for timing diagrams.
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 59 preliminary notes: 1.see table 30 and table 31 for program command sequence. 2.see the section on dq3 for information on the sector erase timer. figure 6. erase operation erase suspend/erase resume commands the erase suspend command, b0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation, in - cluding the 50 s time-out period duri ng the sector erase command sequence. the erase suspend command is ignored if written during the chip erase opera - tion or embedded program algorithm. when the erase suspend command is writte n during the sector erase operation, the device requires a typical of 5 s ( maximum of 20 s) to suspend the erase operation. however, when the erase su spend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. after the erase operation is suspende d, the device enters the erase-sus - pend-read mode. the system can read data from or program data to any sector not selected for erasure. (the device erase suspends all sectors selected for era - sure.) reading at any address within erase-suspended sectors produces status information on dq7?dq0. the system ca n use dq7, or dq6 and dq2 together, to determine if a sector is actively er asing or is erase-suspended. refer to write operation status on page 63 for information on these status bits. after an erase-suspended program operatio n is complete, the device returns to the erase-suspend-read mode. the system can determine the status of the pro - gram operation using the dq7 or dq6 status bits, just as in the standard word program operation. refer to write operation status on page 63 for more information. start write erase command sequence (notes 1, 2) data poll to erasing bank from system data = ffh? no yes erasure completed embedded erase algorithm in progress
60 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary in the erase-suspend-read mode, the system can also issue the autoselect com - mand sequence. refer to the autoselect mode on page 37 and autoselect command sequence on page 51 sections for details. to resume the sector erase operation, the system must write the erase resume command. further writes of the resume command are ignored. another erase suspend command can be written after the chip resumes erasing. note: during an erase operation, this flas h device performs multiple internal operations which are invisible to the system. when an erase operation is suspended, any of the internal operations that were not fully completed must be restarted. as such, if this flas h device is continually issued suspend/resume com - mands in rapid succession, erase progress is impede d as a function of the number of suspends. the re - sult is a longer cumulative erase time than without suspends. note that the additional suspends do not affect device reliability or future performance. in most systems rapi d erase/suspend activity occurs only briefly. in such cases, erase performance is not significantly impacted.
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 61 preliminary command definitions ta b l e 3 0 . command definitions (x16 mode, byte# = v ih ) command sequence ( note 1 ) cycles bus cycles (notes 2 ? 5 ) first second third fourth fifth sixth read ( note 5 ) 1 ra rd reset ( note 6 ) 1 xxx f0 autoselect ( note 7 ) manufacturer id 4 555 aa 2aa 55 555 90 x00 0001 device id ( note 8 ) 6 555 aa 2aa 55 555 90 x01 227e x0e ( note 19 ) x0f ( note 19 ) device id ( note 9 ) 4 555 aa 2aa 55 555 90 x01 ( note 18 ) secured silicon sector factory protect 4 555 aa 2aa 55 555 90 x03 ( note 10 ) sector group protect verify ( note 11 ) 4 555 aa 2aa 55 555 90 (sa)x02 00/01 enter secured silic on sector region 3 555 aa 2aa 55 555 88 exit secured silicon sector region 4 555 aa 2aa 55 555 90 xxx 00 program 4 555 aa 2aa 55 555 a0 pa pd write to buffer ( note 12 ) 3 555 aa 2aa 55 sa 25 sa wc pa pd wbl pd program buffer to flash 1 sa 29 write to buffer abort reset ( note 13 ) 3 555 aa 2aa 55 555 f0 unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program ( note 14 ) 2 xxx a0 pa pd unlock bypass reset ( note 15 ) 2 xxx 90 xxx 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 program/erase suspend ( note 16 ) 1 xxx b0 program/erase resume ( note 17 ) 1 xxx 30 cfi query ( note 18 ) 1 55 98 legend: x = don?t care ra = read address of memory location to be read. rd = read data read from location ra during read operation. pa = program address. addresses latch on falling edge of we# or ce# pulse, whichever happens later. pd = program data for location pa. data latches on rising edge of we# or ce# pulse, wh ichever happens first. sa = sector address of sector to be verified (in autoselect mode) or erased. address bits a21?a15 un iquely select any sector. wbl = write buffer location. address must be within same write buffer page as pa. wc = word count. number of write buffer locations to load minus 1. notes: 1. see table 4 on page 19 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells indicate read cycles. all others are write cycles. 4. during unlock and command cycles, when lo wer address bits are 555 or 2aa as shown in table, address bits above a11 and data b its above dq7 are don?t care. 5. no unlock or command cycles requir ed when device is in read mode. 6. reset command is required to return to re ad mode (or to erase-suspend-read mode if previously in erase suspend) when device i s in autoselect mode, or if dq5 goes high while device is providing status information. 7. fourth cycle of the autoselect command se quence is a read cycle. data bits dq15?dq8 are don?t care. except for rd, pd and wc. see autoselect command sequence on page 51 for more information. 8. for s29gl064a and s29gl032a, device id must be read in three cycles. 9. for s29gl016a, device id must be read in one cycle. 10. refer to table 15 on page 38 for data indicating secured silicon sector factory protect status. 11. data is 00h for an unprotected sector group and 01h for a protected sector group. 12. total number of cycles in command sequen ce is determined by number of words writte n to write buffer. maximum number of cycle s in command sequence is 21, including program buffer to flash command. 13. command sequence resets device for next co mmand after aborted write-to-buffer operation. 14. unlock bypass command is required prior to unlock bypass program command. 15. unlock bypass reset command is required to return to read mode when device is in unlock bypass mode. 16. system may read and program in non-erasing sectors, or enter autoselect mode, when in erase suspend mode. erase suspend comm and is valid only during a sector erase operation. 17. erase resume command is valid only during erase suspend mode. 18. command is valid when device is ready to read array data or when device is in autoselect mode. 19. refer to table 15 on page 38 , for individual device ids per device density and model number.
62 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary ta b l e 3 1 . command definitions (x8 mode, byte# = v il ) command sequence ( note 1 ) cycles bus cycles (notes 2?5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read ( note 6 ) 1 ra rd reset ( note 7 ) 1 xxx f0 autoselect ( note 8 ) manufacturer id 4 aaa aa 555 55 aaa 90 x00 01 device id ( note 9 ) 6 aaa aa 555 55 aaa 90 x02 7e x1c ( note 18 ) x1e ( note 18 ) device id ( note 10 ) 4 aaa aa 555 55 aaa 90 x02 ( note 11 ) secured silicon sector factory protect 4 aaa aa 555 55 aaa 90 x06 ( note 10 ) sector group protect verify ( note 12 ) 4 aaa aa 555 55 aaa 90 (sa)x04 00/01 enter secured silic on sector region 3 aaa aa 555 55 aaa 88 exit secured silicon sector region 4 aaa aa 555 55 aaa 90 xxx 00 write to buffer ( note 13 ) 3 aaa aa 555 55 sa 25 sa bc pa pd wbl pd program buffer to flash 1 sa 29 write to buffer abort reset ( note 14 ) 3 aaa aa 555 55 aaa f0 chip erase 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 sector erase 6 aaa aa 555 55 aaa 80 aaa aa 555 55 sa 30 program/erase suspend ( note 15 ) 1 xxx b0 program/erase resume ( note 16 ) 1 xxx 30 cfi query ( note 17 ) 1 aa 98 legend: x = don?t care ra = read address of memory location to be read. rd = read data read from location ra during read operation. pa = program address. addresses latch on falling edge of we# or ce# pulse, whichever happens later. pd = program data for location pa. data latches on rising edge of we# or ce# pulse, wh ichever happens first. sa = sector address of sector to be verified (in autoselect mode) or erased. address bits a21?a15 un iquely select any sector. wbl = write buffer location. address must be within same write buffer page as pa. bc = byte count. number of write buffer locations to load minus 1. notes: 1. see table 4 on page 19 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells indicate read cycles. all others are write cycles. 4. during unlock and command cycles, when lo wer address bits are 555 or aa a as shown in table, addre ss bits above a11 are don?t care. 5. unless otherwise noted, addre ss bits a21?a11 are don?t cares. 6. no unlock or command cycles requir ed when device is in read mode. 7. reset command is required to return to re ad mode (or to erase-suspend-read mode if previously in erase suspend) when device i s in autoselect mode, or if dq5 goes high while device is providing status information. 8. fourth cycle of autoselect command sequence is a read cycle. data bits dq15?dq8 are don?t care. see autoselect command sequence on page 51 or more information. 9. for s29gl064a and s29gl032a device id must be read in three cycles. 10. for s29gl016a, device id must be read in one cycle. 11. refer to table 15 on page 38 , for data indicating secured silic on sector factory protect status. 12. data is 00h for an unprotected sector group and 01h for a protected sector group. 13. total number of cycles in command sequen ce is determined by number of bytes writte n to write buffer. maximum number of cycle s in command sequence is 37, including program buffer to flash command. 14. command sequence resets device for next co mmand after aborted write-to-buffer operation. 15. system may read and program in non-erasing sectors, or enter autoselect mode, when in erase suspend mode. erase suspend comm and is valid only during a sector erase operation. 16. erase resume command is valid only during erase suspend mode. 17. command is valid when device is ready to read array data or when device is in autoselect mode. 18. refer to table 15 on page 38 , for individual device ids per device density and model number.
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 63 preliminary write operation status the device provides several bits to dete rmine the status of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. ta b l e 32 on page 68 and the follow - ing subsections describe the function of these bits. dq7 and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. the device also provides a ha rdware-based output signal, ry/by#, to determine whether an embedded program or erase operation is in progress or is completed. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whether the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. during the embedded program algorithm, the device outputs on dq7 the com - plement of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. wh en the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a pro - gram address falls within a protected sector, data# polling on dq7 is active for approximately 1 s, then the device returns to the read mode. during the embedded erase algorithm, data# polling produces a 0 on dq7. when the embedded erase algorithm is co mplete, or if the device enters the erase suspend mode, data# polling produces a 1 on dq7. the system must pro - vide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# polling on dq7 is active for approximately 100 s, then the device returns to the read mode. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the se - lected sectors that are protected. howe ver, if the system reads dq7 at an address within a protected sector, the status may not be valid. just prior to the completion of an em bedded program or erase operation, dq7 may change asynchronously with dq0?dq6 while output enable (oe#) is as - serted low. that is, the device may chan ge from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device completed the program or erase operation and dq7 has valid data, the data outputs on dq0?dq6 may be still invalid. valid data on dq0?dq7 appears on successive read cycles. ta b l e 32 on page 68 shows the outputs for data# polling on dq7. figure 7, on page 64 shows the data# polling algorithm. figure 19, on page 80 shows the data# polling timing diagram.
64 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary notes: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = 1 because dq7 may change simultaneously with dq5. figure 7. data# polling algorithm ry/by#: r ea dy /bu sy# the ry/by# is a dedicated, open-drain output pin which indicates whether an embedded algorithm is in progress or comp lete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-drain output, several ry/by# pi ns can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the device is actively erasing or programming. (this includes programming in the erase susp end mode.) if the output is high (ready), the device is in the read mode , the standby mode, or in the erase-sus - pend-read mode. ta b l e 32 on page 68 shows the outputs for ry/by#. dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq15?dq0 addr = va read dq15?dq0 addr = va dq7 = data? start
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 65 preliminary dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whethe r the device entered the erase suspend mode. toggle bit i may be read at any addr ess, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm operation, successive read cy - cles to any address cause dq6 to toggle. the system may use either oe# or ce# to control the read cycles. when the op eration is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approximately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algo - rithm erases the unprotected sectors, an d ignores the selected sectors that are protected. the system can use dq6 and dq2 together to determine whether a sector is ac - tively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alter - natively, the system can use dq7 (see the subsection on dq7: data# polling on page 63 ). if a program address falls within a protected sector, dq6 toggles for approxi - mately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. ta b l e 32 on page 68 shows the outputs for toggle bit i on dq6. figure 8, on page 66 shows the toggle bit algorithm. figure 20, on page 81 shows the toggle bit timing diagrams. figure 21, on page 81 shows the differences between dq2 and dq6 in graphical form. see also the subsection on dq2: toggle bit ii on page 67 .
66 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary note: the system should recheck the toggle bit even if dq5 = 1 because the toggle bit may stop tog - gling as dq5 changes to 1 . see the subsections on dq6 and dq2 for more information. figure 8. to g g l e b i t a l g o r i t h m start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete read dq7?dq0 toggle bit = toggle? read dq7?dq0 twice read dq7?dq0
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 67 preliminary dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that were selected for erasure. (the system may us e either oe# or ce# to control the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, in dicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to ta b l e 32 on page 68 to compare outputs for dq2 and dq6. figure 8, on page 66 shows the toggle bit algorithm in flowchart form, and the section ?dq2: toggle bit ii? explains the algorithm. see also the ry/by#: ready/ busy# subsection. figure 20, on page 81 shows the toggle bit timing diagram. figure 21, on page 81 shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to figure 8, on page 66 for the following discussion. whenever the system initially begins reading togg le bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new valu e of the toggle bit with the first. if the toggle bit is not toggling, the device completed the program or erase oper - ation. the system can read array data on dq7?dq0 on the following read cycle. however, if after the initial two read cycles, the system determines that the tog - gle bit is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is , the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device success - fully completed the program or erase operat ion. if it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as de - scribed in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algo - rithm when it returns to determine the status of the operation (top of figure 8, on page 66 ). dq5: exceeded timing limits dq5 indicates whether the pr ogram, erase, or write-to-buffer time exceeded a specified internal pulse count limit. un der these conditions dq5 produces a 1 . indicating that the program or erase cycle was not successfully completed. the device may output a 1 on dq5 if the system tries to program a 1 to a location that was previously programmed to 0 . only an erase operation can change a 0 back to a 1. under this condition, the device halts the operation, and when the timing limit is exceeded, dq5 produces a 1 .
68 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary in all these cases, the system must write the reset command to return the device to the reading the array (or to erase-susp end-read if the device was previously in the erase-suspend-program mode). dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not erasure began. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. when the time-out period is complete, dq3 switches from a 0 to a 1 . if the time be - tween additional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor dq3. see also the sector erase command sequence section. after the sector erase command is written, the system should read the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device accepted the command sequence, and then read dq3. if dq3 is 1 , the embedded erase algo - rithm has begun; all further commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is 0 , the device accepts additional sector erase commands. to ensure the command is accepted, the system software should check the status of dq3 prior to and following each subsequent sector erase command. if dq3 is high on the second status check, the last command might not have been accepted. ta b l e 32 on page 68 shows the status of dq3 relative to the other status bits. dq1: write-to-buffer abort dq1 indicates whether a write-to-buffer operation was aborted. under these conditions dq1 produces a 1 . the system must issue the write-to-buffer-abort- reset command sequence to return the device to reading array data. see write buffer on page 21 for more details. notes: 1. dq5 switches to 1 when an embedded program, embedded erase, or write-to-buffer operation exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status inform ation. refer to the appropriate subsection for further details. 3. the data# polling algorithm should be used to moni tor the last loaded write-buffer address location. 4. dq1 switches to 1 when the device aborts the write-to-buffer operation. table 32. write operation status status dq7 ( note 2 ) dq6 dq5 ( note 1 ) dq3 dq2 ( note 2 ) dq1 ry/by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 0 embedded erase algorithm 0 toggle 0 1 toggle n/a 0 program suspend mode program- suspend read program-suspended sector invalid (not allowed) 1 non-program suspended sector data 1 erase suspend mode erase- suspend read erase-suspended sector 1 no toggle 0 n/a toggle n/a 1 non-erase suspended sector data 1 erase-suspend-program (embedded program) dq7# toggle 0 n/a n/a n/a 0 write-to- buffer busy ( note 3 )dq7#toggle0n/an/a00 abort ( note 4 )dq7#toggle0n/an/a10
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 69 preliminary absolute maximum ratings storage temperature, plastic packages . . . . . . . . . . . . . . . . ?65c to +150c ambient temperature with power applied . . . . . . . . . . . . . . ?65c to +125c voltage with respect to ground: v cc ( note 1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +4.0 v a9, oe#, acc and reset# ( note 2 ) . . . . . . . . . . . . . ?0.5 v to +12.5 v all other pins ( note 1 ) . . . . . . . . . . . . . . . . . . . . . ?0.5 v to v cc +0.5 v output short circuit current ( note 3 ) . . . . . . . . . . . . . . . . . . . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/os is ?0.5 v. during voltage transitions, inputs or i/os may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 9, on page 69 . maximum dc voltage on input or i/os is v cc + 0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc + 2.0 v for periods up to 20 ns. see figure 10, on page 69 . 2. minimum dc input voltage on pins a9, oe #, acc, and reset# is ?0.5 v. during voltage transitions, a9, oe#, a cc, and reset# may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 9, on page 69 . maximum dc input voltage on pin a9, oe#, acc, and reset# is +12.5 v which may overshoot to +14.0v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. 4. stresses above those listed under absolute maximum ratings may cause permanent damage to th e device. this is a stress rati ng only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions fo r extended periods may affect device reliability. figure 9. maximum negative overshoot waveform figure 10. maximum positive overshoot waveform 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v
70 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary operating ranges industrial (i) devices ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . ?40c to +85c supply voltages v cc for full voltage range . . . . . . . . . . . . . . . . . . . . . . . . . +2.7 v to +3.6 v v cc for regulated voltage range . . . . . . . . . . . . . . . . . . . . . +3.0 v to +3.6 v v io . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v cc note: operating ranges define those lim its between which the functionalit y of the device is guaranteed .
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 71 preliminary dc characteristics cmos compatible notes: 1. on the wp#/acc pin only, the maximum input load current when wp# = v il is 5.0 a. 2. the i cc current listed is typically less than 3.5 ma/mhz, with oe# at v ih . 3. maximum i cc specifications are tested with v cc = v cc max. 4. i cc active while embedded erase or embedded program is in progress. 5. automatic sleep mode enable s the low power mode when addresses remain stable for t acc + 30 ns. 6. v cc voltage requirements. 7. not 100% tested. parameter symbol parameter description (notes) test conditions min typ max unit i li input load current ( note 1 ) v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9, acc input load current v cc = v cc max ; a9 = 12.5 v -40c to 0c 250 a 0c to 85c 35 i lr reset leakage current v cc = v cc max ; reset# = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i cc1 v cc initial read current ( notes 2 , 3 ) ce# = v il, oe# = v ih , 1 mhz 520 ma 5 mhz 18 25 10 mhz 35 50 i cc2 v cc intra-page read current ( notes 2 , 3 ) ce# = v il, oe# = v ih 10 mhz 520 ma 40 mhz 10 40 i cc3 v cc active write current ( note 3 ) ce# = v il, oe# = v ih 50 60 ma i cc4 v cc standby current ( note 3 ) ce#, reset# = v cc 0.3 v, wp# = v ih 15a i cc5 v cc reset current ( note 3 ) reset# = v ss 0.3 v, wp# = v ih 15a i cc6 automatic sleep mode ( notes 3 , 5 ) v ih = v cc 0.3 v; -0.1< v il 0.3 v, wp# = v ih 15a v il input low voltage 1 ( note 6 ) ?0.5 0.8 v v ih input high voltage 1 ( note 6 ) 0.7 v cc v cc + 0.5 v v hh voltage for acc program acceleration v cc = 2.7 ?3.6 v 11.5 12.0 12.5 v v id voltage for autoselect and temporary sector unprotect v cc = 2.7 ?3.6 v 11.5 12.0 12.5 v v ol output low voltage ( note 6 ) i ol = 4.0 ma, v cc = v cc min 0.45 v v oh1 output high voltage i oh = ?2.0 ma, v cc = v cc min 0.85 v cc v v oh2 i oh = ?100 a, v cc = v cc min v cc ?0.4 v v lko low v cc lock-out voltage ( note 7 ) 2.3 2.5 v
72 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary test conditions note: diodes are in3064 or equivalent. figure 11. te s t s e t u p key to switching waveforms figure 12. input waveforms and measurement levels table 33. test specifications test condition all speeds unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 5 ns input pulse levels 0.0 or v cc v input timing measuremen t reference levels 0.5 v cc v output timing measurement reference levels 0.5 v cc v waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permi tted changing, state unknown does not apply center line is high impedance state (high z) 2.7 k c l 6.2 k 3.3 v device under tes t v cc 0.0 v output measurement level input 0.5 v cc 0.5 v cc
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 73 preliminary ac characteristics notes: 1. not 100% tested. 2. see figure 11, on page 72 and table 33 on page 72 for test specifications notes: 1. not 100% tested. 2. see figure 11, on page 72 and table 33 on page 72 for test specifications. table 34. read-only operations-s29gl064a only parameter description test setup speed options unit jedec std. 90 10 11 t avav t rc read cycle time ( note 1 ) min 90 100 110 ns t avqv t acc address to output delay ce#, oe# = v il max 90 100 110 ns t elqv t ce chip enable to output delay oe# = v il max 90 100 110 ns t pacc page access time max 25 30 30 ns t glqv t oe output enable to output delay max 25 30 30 ns t ehqz t df chip enable to output high z ( note 1 ) max 16 ns t ghqz t df output enable to output high z ( note 1 ) max 16 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t oeh output enable hold time ( note 1 ) read min 0 ns toggle and data# polling min 10 ns ta b l e 3 5 . read-only operations-s29gl032a only parameter description test setup speed options unit jedec std. 90 10 11 t avav t rc read cycle time ( note 1 ) min 90 100 110 ns t avqv t acc address to output delay ce#, oe# = v il max 90 100 110 ns t elqv t ce chip enable to output delay oe# = v il max 90 100 110 ns t pacc page access time max 25 30 30 ns t glqv t oe output enable to output delay max 25 30 30 ns t ehqz t df chip enable to output high z ( note 1 ) max 16 ns t ghqz t df output enable to output high z ( note 1 ) max 16 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t oeh output enable hold time ( note 1 ) read min 0 ns toggle and data# polling min 10 ns
74 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary notes: 1. not 100% tested. 2. see figure 11, on page 72 and table 33 on page 72 for test specifications. figure 13. read operation timings note: * figure shows device in word mode. addresses are a1?a-1 for byte mode . table 36. read-only operation-s29gl016a only parameter description test setup speed options unit jedec std. 90 10 t avav t rc read cycle time ( note 1 ) min 90 100 ns t avqv t acc address to output delay ce#, oe# = v il max 90 100 ns t elqv t ce chip enable to output delay oe# = v il max 90 100 ns t pacc page access time max 25 30 ns t glqv t oe output enable to output delay max 25 30 ns t ehqz t df chip enable to output high z ( note 1 ) max 16 ns t ghqz t df output enable to output high z ( note 1 ) max 16 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t oeh output enable hold time ( note 1 ) read min 0 ns toggle and data# polling min 10 ns t oh t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t rh t oe t rh 0 v ry/by# reset# t df a23 - a2 ce# oe# a1 - a0* data bus same page aa ab ac ad qa qb qc qd t acc t pac c t pac c t pac c
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 75 preliminary figure 14. page read timings note: not 100% tested . notes: 1. not 100% tested. 2. see the erase and programming performance on page 87 for more information. 3. for 1?16 words/1?32 bytes programmed. figure 15. reset timings ta b l e 3 7 . hardware reset (reset#) parameter description all speed options unit jedec std. t ready reset# pin low (during embedded algorithms) to read mode ( see note ) max 20 s t ready reset# pin low (not during embedded algorithms) to read mode ( see note ) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read ( see note ) min 50 ns t rpd reset# input low to standby mode ( see note ) min 20 s t rb ry/by# output high to ce#, oe# pin low min 0 ns reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp t rb t rh
76 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary notes: 1. not 100% tested. 2. see the erase and programming performance on page 87 for more information. 3. for 1?16 words/1?32 bytes programmed. 4. if a program suspend command is issued within t poll , the device requires t poll before reading status data, once programming resumes (that is, the program resume command is writte n). if the suspend command was issued after t poll , status data is available immediately after programming resumes. see figure 16, on page 79 . table 38. erase and program operations-s29gl064a parameter description speed options unit jedec std. 90 10 11 t avav t wc write cycle time ( note 1 ) min 90 100 110 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low du ring toggle bit polling min 15 ns t wlax t ah address hold time min 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 35 ns t whdx t dh data hold time min 0 ns t ceph ce# high during toggle bit polling min 20 ns t oeph oe# high during togg le bit polling min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 ns t whdl t wph write pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation ( note 2 , note 3 ) typ 240 s single word prog ram operation ( note 2 )typ60 accelerated single word program operation ( note 2 )typ 54 t whwh2 t whwh2 sector erase operation ( note 2 )typ0.5sec t vhh v hh rise and fall time ( note 1 ) min 250 ns t vcs v cc setup time note 1 )min50s t busy we# high to ry/by# low min 90 100 110 ns t poll program valid before status polling max 4 s
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 77 preliminary notes: 1. not 100% tested. 2. see erase and programming performance on page 87 for more information 3. for 1?16 words/1?32 bytes programmed. 4. effective write buffer specific ation is based upon a 16-word/32-byte write buffer operation. 5. if a program suspend command is issued within t poll , the device requires t poll before reading status data, once programming resumes (that is, the program resume command is writte n). if the suspend command was issued after t poll , status data is available immediately after programming resumes. see figure 16, on page 79 . table 39. erase and program operations-s29gl032a only parameter description speed options unit jedec std. 90 10 11 t avav t wc write cycle time ( note 1 ) min 90 100 110 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 35 ns t whdx t dh data hold time min 0 ns t ceph ce# high during toggle bit polling min 20 ns t oeph oe# high during toggle bit polling min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 ns t whdl t wph write pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation ( note 2 , note 3 ) typ 240 s single word program operation ( note 2 ) ty p 6 0 accelerated single word program operation ( note 2 ) ty p 5 4 t whwh2 t whwh2 sector erase operation ( note 2 ) ty p 0 . 5 se c t vhh v hh rise and fall time ( note 1 ) min 250 ns t vcs v cc setup time ( note 1 ) min 50 s t busy we# high to ry/by# low min 90 100 110 ns t poll program valid before status polling max 4 s
78 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary notes: 1. not 100% tested. 2. see erase and programming performance on page 87 for more information 3. for 1?16 words/1?32 bytes programmed. 4. effective write buffer specific ation is based upon a 16-word/32-byte write buffer operation. 5. if a program suspend command is issued within t poll , the device requires t poll before reading status data, once programming resumes (that is, the program resume command is writte n). if the suspend command was issued after t poll , status data is available immediately after programming resumes. see figure 16, on page 79 table 40. erase and program operations-s29gl016a only parameter description speed options unit jedec std. 90 10 t avav t wc write cycle time ( note 1 ) min 90 100 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 35 ns t whdx t dh data hold time min 0 ns t ceph ce# high during toggle bit polling min 20 ns t oeph oe# high during toggle bit polling min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 ns t whdl t wph write pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation ( note 2 , note 3 ) typ 240 s single word program operation ( note 2 ) typ 60 accelerated single word program operation ( note 2 ) typ 54 t whwh2 t whwh2 sector erase operation ( note 2 ) typ 0.5 sec t vhh v hh rise and fall time ( note 1 ) min 250 ns t vcs v cc setup time ( note 1 ) min 50 s t busy we# high to ry/by# low min 90 100 ns t poll program valid before status polling max 4 s
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 79 preliminary notes: 1. pa = program address, pd = program data, d out is the true data at the program address. 2. illustration shows device in word mode. figure 16. program operation timings figure 17. accelerated program timing diagram oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t poll t cs status d out ry/by# t rb t busy t ch pa program command sequence (last two cycles) acc t vhh v hh v il or v ih v il or v ih t vhh acc t vhh v hh v il or v ih v il or v ih t vhh
80 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary notes: 1. sa = sector address (for sector erase), va = valid address for reading status data (see write operation status on page 63 .) 2. illustration shows device in word mode. figure 18. chip/sector erase operation timings note: va = valid address. illustration shows first status cycle a fter command sequence, last status read cycle, and array data read cycle. figure 19. data# polling timings (during embedded algorithms) oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy we# ce# oe# high z t oe high z dq7 dq0?dq6 ry/by# t busy complement tr u e addresses va t ch va va status data complement status data tr u e valid data valid data t poll t acc t ce t oeh t df t oh t rc
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 81 preliminary note: va = valid address; not required for dq 6. illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. figure 20. toggle bit timings (during embedded algorithms) note: dq2 toggles only when read at an address within an erase- suspended sector. the system may use oe# or ce# to toggle dq2 and dq6. figure 21. dq2 vs. dq6 note: not 100% tested. ta b l e 4 1 . temporary sector unprotect parameter description all speed options unit jedec std t vidr v id rise and fall time ( see note ) min 500 ns t rsp reset# setup time for temporary sector unprotect min 4 s oe# ce# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq6 / dq2 valid data valid status valid status valid status ry/by# enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
82 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary figure 22. temporary sector group unprotect timing diagram note: for sector group protect, a6:a0 = 0xx0010. for sector group unprotect, a6:a0 = 1xx0010. figure 23. sector group protect and unprotect timing diagram reset# t vidr v id v ss , v il , or v ih v id v ss , v il , or v ih ce# we# ry/by# t vidr t rsp program or erase command sequence t rrb sector group protect: 150 s, sector group unprot ect: 15 ms 1 s reset# sa, a6, a3, a2, a1, a0 data ce# we# oe# 60h 60h 40h valid* valid* valid* status sector group protect or unprotect verify v id v ih
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 83 preliminary notes: 1. not 100% tested. 2. see the erase and programming performance on page 87 for more information. 3. for 1?16 words/1?32 bytes programmed. 4. if a program suspend command is issued within t poll , the device requires t poll before reading status data, once programming resumes (that is, the program resume command is writte n). if the suspend command was issued after t poll , status data is available immediately after programming resumes. see figure 24, on page 86 . table 42. alternate ce# controlled er ase and program operations-s29gl064a parameter description speed options unit jedec std. 90 10 11 t avav t wc write cycle time ( note 1 ) min 90 100 110 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 45 ns t dveh t ds data setup time min 35 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 35 ns t ehel t cph ce# pulse width high min 25 ns t whwh1 t whwh1 write buffer program operation ( notes 2 , 3 ) typ 240 s single word program operation ( note 2 )typ60 accelerated single word program operation ( note 2 )typ 54 t whwh2 t whwh2 sector erase operation ( note 2 )typ0.5sec t rh reset# high time before write min 50 ns t poll program valid before status polling ( note 4 )max4 s
84 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary notes: 1. not 100% tested. 2. see erase and programming performance on page 87 for more information 3. for 1?16 words/1?32 bytes programmed. 4. if a program suspend command is issued within t poll , the device requires t poll before reading status data, once programming resumes (that is, the program resume command is writte n). if the suspend command was issued after t poll , status data is available immediately after programming resumes. see figure 24, on page 86 . table 43. alternate ce# controlled er ase and program operations-s29gl032a parameter description speed options unit jedec std. 90 10 11 t avav t wc write cycle time ( note 1 ) min 90 100 110 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 45 ns t dveh t ds data setup time min 35 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 35 ns t ehel t cph ce# pulse width high min 25 ns t whwh1 t whwh1 write buffer program operation ( notes 2 , 3 ) typ 2 40 s single word program operation ( note 2 ) typ 6 0 accelerated single word program operation ( note 2 ) typ 5 4 t whwh2 t whwh2 sector erase operation ( note 2 ) typ 0.5 sec t rh reset# high time before write min 50 ns t poll program valid before status polling ( note 4 ) max 4 s
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 85 preliminary notes: 1. not 100% tested. 2. see erase and programming performance on page 87 for more information 3. for 1?16 words/1?32 bytes programmed. 4. if a program suspend command is issued within t poll , the device requires t poll before reading status data, once programming resumes (that is, the program resume command is writte n). if the suspend command was issued after t poll , status data is available immediately after programming resumes. see figure 24, on page 86 table 44. alternate ce# controlled erase and program operations-s29gl016a parameter description speed options unit jedec std. 90 10 t avav t wc write cycle time ( note 1 ) min 90 100 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 45 ns t dveh t ds data setup time min 35 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 35 ns t ehel t cph ce# pulse width high min 25 ns t whwh1 t whwh1 write buffer program operation ( note 2 , note 3 ) typ 240 s single word program operation ( note 2 ) ty p 6 0 accelerated single word program operation ( note 2 ) ty p 5 4 t whwh2 t whwh2 sector erase operation ( note 2 ) ty p 0 .5 se c t rh reset# high time before write min 50 ns t poll program valid before status polling ( note 4 ) max 4 s
86 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary notes: 1. figure indicates last two bus cycles of a program or erase operation. 2. pa = program address, sa = sector address, pd = program data. 3. dq7# is the complement of the data written to the device. d out is the data written to the device. 4. illustration shows device in word mode figure 24. alternate ce# controlled write (e rase/program) operation timings t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling pbd for program 55 for erase t rh t whwh1 or 2 t poll ry/by# t wh 29 for program buffer to flash 30 for sector erase 10 for chip erase pba for program 2aa for erase sa for program buffer to flash sa for sector erase 555 for chip erase t busy
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 87 preliminary erase and programming performance notes: 1. typical program and erase times as sume the following conditions: 25 c, v cc = 3.0v, 10,000 cycles; chec kerboard data pattern. 2. under worst case conditions of 90 c; worst case v cc , 100,000 cycles. 3. effective programming time (typ) is 15 s (per word), 7.5 s (per byte). 4. effective accelerated programming time (typ) is 12.5 s (per word), 6.3 s (per byte). 5. effective write buffer specification is ca lculated on a per-word/per-byte basis for a 16-word/32-byte write buffer operation. 6. in the pre-programming step of the embedded erase algorithm, all bits are programmed to 00h before erasure. 7. system-level overhead is the time required to execute the command sequence(s) for the program command. see table 30 on page 61 and table 31 on page 62 for further information on command definitions. notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. parameter typ ( note 1 ) max ( note 2 ) unit comments sector erase time 0.5 3.5 sec excludes 00h programming prior to erasure ( note 6 ) chip erase time s29gl016a 17.5 35 s29gl032a 32 64 s29gl064a 64 128 total write buffer program time ( notes 3 , 5 )240 s excludes system level overhead ( note 7 ) total accelerated effective write buffer program time ( notes 4 , 5 ) 200 chip program time s29gl016a 16 sec s29gl032a 31.5 s29gl064a 63 ta b l e 4 5 . tsop pin and bga package capacitance parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 tsop 6 7.5 pf bga 4.2 5.0 pf c out output capacitance v out = 0 tsop 8.5 12 pf bga 5.4 6.5 pf c in2 control pin capacitance v in = 0 tsop 7.5 9 pf bga 3.9 4.7 pf
88 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary physical dimensions ts048?48-pin standard thin small outline package (tsop) -x- x = a or b e/2 detail b c l 0.25mm (0.0098") bsc 0? detail a r gage line parallel to seating plane b b1 (c) 7 6 c1 with plating base metal 7 c a-b s m 0.08mm (0.0031") section b-b e 0.10 c a2 plane seating c a1 see detail b s e e d e t a i l b b b b b see detail a s e e d e t a i l a 2 standard pin out (top view) 2 n +1 n n 1 4 2 a -a- -b- 5 9 e 5 d1 d 6 2 3 4 5 7 8 9 ts 048 mo-142 (b) ec 48 min 0.05 0.95 0.17 0.17 0.10 0.10 18.30 19.80 0.50 0? 0.08 11.90 0.50 basic max 0.15 1.20 0.27 0.16 0.21 5? 0.20 18.50 12.10 0.70 20.20 0.23 1.05 0.20 1.00 0.22 18.40 20.00 0.60 3? 12.00 nom symbol jedec package b1 a2 a1 a d l e e d1 b c1 c 0 r n 1 notes: controlling dimensions are in millimeters (mm). (dimensioning and tolerancing conforms to ansi y14.5m-1982) pin 1 identifier for standard pin out (die up). not applicable. to be determined at the seating plane -c- . the seating plane is defined as the plane of contact that is made when the package leads are allowed to rest freely on a flat horizontal surface. dimensions d1 and e do not include mold protrusion. allowable mold protusion is 0.15mm (.0059") per side. dimension b does not include dambar protusion. allowable dambar protusion shall be 0.08 (0.0031") total in excess of b dimension at max. material condition. minimum space between protrusion and an adjacent lead to be 0.07 (0.0028"). these dimensions apply to the flat section of the lead between 0.10mm (.0039") and 0.25mm (0.0098") from the lead tip. lead coplanarity shall be within 0.10mm (0.004") as measured from the seating plane. dimension "e" is measured at the centerline of the leads. 3325 \ 16-038.10a
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 89 preliminary ts056?56-pin standard thin small outline package (tsop) 6 2 3 4 5 7 8 9 ts 056 mo-142 (d) ec 56 min 0.05 0.95 0.17 0.17 0.10 0.10 18.30 19.80 0.50 0? 0.08 13.90 0.50 basic max 0.15 1.20 0.27 0.16 0.21 8? 0.20 18.50 14.10 0.70 20.20 0.23 1.05 0.20 1.00 0.22 18.40 20.00 0.60 14.00 nom symbol jedec package b1 a2 a1 a d l e e d1 b c1 c 0 r n 1 notes: controlling dimensions are in millimeters (mm). (dimensioning and tolerancing conforms to ansi y14.5m-1982) pin 1 identifier for reverse pin out (die up). pin 1 identifier for reverse pin out (die down), ink or laser mark. to be determined at the seating plane -c- . the seating plane is defined as the plane of contact that is made when the package leads are allowed to rest freely on a flat horizontal surface. dimensions d1 and e do not include mold protrusion. allowable mold protusion is 0.15mm (.0059") per side. dimension b does not include dambar protusion. allowable dambar protusion shall be 0.08 (0.0031") total in excess of b dimension at max. material condition. minimum space between protrusion and an adjacent lead to be 0.07 (0.0028"). these dimensions apply to the flat section of the lead between 0.10mm (.0039") and 0.25mm (0.0098") from the lead tip. lead coplanarity shall be within 0.10mm (0.004") as measured from the seating plane. dimension "e" is measured at the centerline of the leads. n +1 2 n 1 2 n 3 reverse pin out (top view) c e a1 a2 2x (n/2 tips) 0.10 9 seating plane a see detail a b b ab e d1 d 2x 2x (n/2 tips) 0.25 2x 0.10 0.10 n 5 +1 n 2 4 5 1 n 2 2 standard pin out (top view) see detail b detail a (c) ? l 0.25mm (0.0098") bsc c r gauge plane parallel to seating plane b b1 (c) 7 6 c1 with plating base metal 7 0.08mm (0.0031") m c a - b s section b-b detail b x e/2 x = a or b 3356 \ 16-038.10c
90 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary laa064?64-ball fortified ball grid array (bga)
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 91 preliminary vbn048?48-ball fine-pitch ball grid array (bga) 10x 6 mm package 3425\ 16-038.25 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls. 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. package vbn 048 jedec n/a 10.00 mm x 6.00 mm nom package symbol min nom max note a --- --- 1.00 overall thickness a1 0.17 --- --- ball height a2 0.62 --- 0.73 body thickness d 10.00 bsc. body size e 6.00 bsc. body size d1 5.60 bsc. ball footprint e1 4.00 bsc. ball footprint md 8 row matrix size d direction me 6 row matrix size e direction n 48 total ball count b 0.35 --- 0.45 ball diameter e 0.80 bsc. ball pitch sd / se 0.40 bsc. solder ball placement none depopulated solder balls +0.20 -0.50 1.00 -0.50 +0.20 1.00 ?0.50 seating plane a1 id. a1 corner a2 a ?b e d e b a m ?0.15 c m 7 7 6 e se sd c 0.10 a1 c 6 5 4 3 2 a b c d e f g 1 h b a c 0.08 e1 d1 c ?0.08
92 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary vbk048?ball fine-pitch ball grid array (bga) 8.15x 6.15 mm package 3338 \ 16-038.25 \ 10.05.04 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls. 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. side view top view seating plane a2 a (4x) 0.10 10 d e c 0.10 a1 c b a c 0.08 bottom view a1 corner b a m 0.15 c m 7 7 6 e se sd 6 5 4 3 2 a b c d e f g 1 h b e1 d1 c 0.08 pin a1 corner index mark package vbk 048 jedec n/a 8.15 mm x 6.15 mm nom package symbol min nom max note a --- --- 1.00 overall thickness a1 0.18 --- --- ball height a2 0.62 --- 0.76 body thickness d 8.15 bsc. body size e 6.15 bsc. body size d1 5.60 bsc. ball footprint e1 4.00 bsc. ball footprint md 8 row matrix size d direction me 6 row matrix size e direction n 48 total ball count b 0.35 --- 0.43 ball diameter e 0.80 bsc. ball pitch sd / se 0.40 bsc. solder ball placement --- depopulated solder balls
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 93 preliminary vbu056?ball fine-pitch ball grid array (bga) 9 x 7 mm package 3440\ 16-038.25 \ 01.13.05 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls. 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. package vbu 056 jedec n/a 9.00 mm x 7.00 mm nom package symbol min nom max note a --- --- 1.00 overall thickness a1 0.17 --- --- ball height a2 0.62 --- 0.76 body thickness d 9.00 bsc. body size e 7.00 bsc. body size d1 5.60 bsc. ball footprint e1 5.60 bsc. ball footprint md 8 row matrix size d direction me 8 row matrix size e direction n 56 total ball count b 0.35 0.40 0.45 ball diameter e 0.80 bsc. ball pitch sd / se 0.40 bsc. solder ball placement a1,a8,d4,d5,e4,e5,h1,h8 depopulated solder balls seating plane e1 7 se d1 e a c db e f g h 7 8 6 5 3 2 1 e 4 a1 corner 7 sd bottom view c c a d e c 0.05 (2x) c 0.05 b (2x) c 10 side view top view index mark a1 a a2 a1 corner 0.10 0.08 b a c m m c 0.08 0.15 6 nx b
94 s29gl-a mirrorbit? flash family s29gl-a_00_a5 january 11, 2006 preliminary revision summary revision a (october 13, 2004) initial release. revision a1 (december 17, 2004) secured silicon sector flash memory region updated secured silicon sector address table with addresses in x8-mode. dc characteristics (cmos compatible) i lit re-specified over temperature. corrected wp#/acc input load current footnote. revision a2 (january 28, 2005) global: added s29gl032a information. revision a3 (april 22, 2005) added s29gl016a information. corrected secured silicon sector indicator bit in table 15 . revision a4 (july 29, 2005) corrected s29gl032a fine-pitch bga package description from vbn048 to vbk048. corrected s29gl016a information in table 15. corrected s29gl016a information in table 17. updated ordering information and valid combinations for s29gl016a, s29gl032a, and s29gl064a. added requir ements for mcp cellular handsets. added vbu056 connection diagram and vbu056 package dimension drawings revision a5 (january 11, 2006) added model numbers 01 and 02 to ordering information section and autoselect codes table. corrected sector address bit range in s29gl064a table for models r3, w3 and table for models r4 and w4. replaced model numbers w1, w2 with w3, w4 in dq7 to dq0 section of sector address table.
january 11, 2006 s29gl-a_00_a5 s29gl-a mirrorbit? flash family 95 preliminary colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, personal use, and househol d use, but are not designed, deve loped and manufactured as contem plated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and c ould lead directly to death, personal injury, severe physical damage or other lo ss (i.e., nuclear reaction control in nucle ar facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch co ntrol in weapon system), or (2) for any use where chance of failure is intolerabl e (i.e., submersible repeater and artificial satellite). please note that spansion will not be lia ble to you and/or any third party for any claims or damages ari sing in connection with above-men- tioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, dam age or loss from such failures by incorporating safety design measures in to your facility and equipment such as redu ndancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain re strictions on export under the foreign exchange and foreign trade law of japan, the us export administration regulations or the applicable laws of any oth er country, the prior au- thorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subject to change without notice. this document may contain information on a spansion product under development by spansion llc. spansion llc reserves the right to change or discontinue work on any product without notice. the information in t his document is provided as is without warranty or guarantee of any kind as to its ac curacy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty , express, implied, or stat utory. spansion llc assumes no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2004 ? 2006 spansion llc. all rights reserved. spansion, the spansion logo, mirrorbit, combinations thereof, and ex pressflash are trademarks of spansion llc. other company and product names used in this publication are for identification purposes only and may be trade marks of their respective companies.

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